A power and area-efficient pulse-amplitude modulation 4 (PAM-4) transmitter using 3-tap feed-forward equalizer (FFE) based on a slow-wave transmission line is presented. Passive delay line is adopted for generating equalizer tap to overcome the high clocking power consumption. The transmission line achieves high slow-wave factor of 15 with double floating metal shields around the differential coplanar waveguide. The physical dimensions of the transmission line are determined to have low loss and a high slow-wave factor with a small chip area by optimization with 3-D electromagnetic simulations. The transmitter includes 4:1 multiplexers (MUXs) and a quadrature clock generator for high-speed data generation in a quarter-rate system. The 4:1 MUX utilizes 2-UI pulse generator and the input configuration is determined by qualitative analysis. The chip is fabricated in 65-nm CMOS technology and occupies area of 0.151 mm2. The proposed transmitter system exhibits the energy efficiency of 3.03 pJ/b at the data rate of 48 Gb/s with PAM-4 signaling.

中文翻译：

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基于 65 纳米 CMOS 中双屏蔽共面波导的具有 3 抽头 FFE 的 48 Gb/s PAM-4 发射器

提出了一种使用基于慢波传输线的 3 抽头前馈均衡器 (FFE) 的功率和面积高效的脉冲幅度调制 4 (PAM-4) 发射器。采用无源延迟线产生均衡器抽头，以克服高时钟功耗。传输线通过差分共面波导周围的双浮动金属屏蔽实现了 15 的高慢波系数。通过 3-D 电磁仿真优化，确定传输线的物理尺寸具有低损耗和高慢波系数以及小芯片面积。发送器包括 4:1 多路复用器 (MUX) 和正交时钟发生器，用于在四分之一速率系统中生成高速数据。4:1 MUX 采用 2-UI 脉冲发生器，输入配置由定性分析确定。该芯片采用 65 纳米 CMOS 技术制造，占地面积为 0.151 平方毫米。所提出的发射机系统在使用 PAM-4 信令的 48 Gb/s 数据速率下表现出 3.03 pJ/b 的能量效率。