In this work, we investigate for the first time the impact of Negative Capacitance FinFET (NC-FinFET) technology on the performance of processors under the effects of process variations for various operating voltages. The industry compact model of FinFETs (BSIM-CMG) is fully calibrated to reproduce Intel 14nm FinFET data of high volume manufacturing process. A physics-based negative capacitance (NC) model is integrated and solved self-consistently within the BSIM-CMG model. This allows the creation of NC-FinFET standard cell libraries, while considering the effects of various variability sources both in the ferroelectric layer as well as in the underlying constituent FinFET device. The variability-aware NC-FinFET libraries, fully compatible with the existing standard design flow of circuits, are then employed to perform simulations using commercial statistical timing analysis tools in order to study the performance of a 14nm processor. For comprehensive analysis and comparisons, our implementation is done for both NC-FinFET and conventional (baseline) FinFET for a wide range of voltages. Our results demonstrate that process variations have a larger impact on the processor’s performance in NC-FinFET – when it operates at a lower voltage compared to the baseline FinFET that still operates at the nominal high voltage – due to the additional ferroelectric-induced variability. Results also reveal that neglecting process variations leads to overestimating the benefit that NC brings to the processor’s frequency improvement because of the larger timing guardband that is needed to overcome variability in NC-FinFET.

中文翻译：

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负电容 FinFET 技术中可变性对处理器性能的影响

在这项工作中，我们首次研究了负电容 FinFET (NC-FinFET) 技术在各种工作电压的工艺变化影响下对处理器性能的影响。FinFET 的行业紧凑模型 (BSIM-CMG) 经过全面校准，可重现英特尔 14 纳米 FinFET 大批量制造工艺的数据。基于物理的负电容 (NC) 模型在 BSIM-CMG 模型中集成并自洽求解。这允许创建 NC-FinFET 标准单元库，同时考虑铁电层以及底层组成 FinFET 器件中各种可变性源的影响。可变性感知 NC-FinFET 库，与现有的标准电路设计流程完全兼容，然后使用商业统计时序分析工具进行模拟，以研究 14 纳米处理器的性能。为了进行全面的分析和比较，我们对 NC-FinFET 和传统（基线）FinFET 的各种电压进行了实施。我们的结果表明，工艺变化对 NC-FinFET 中处理器的性能有更大的影响——与仍然在标称高电压下工作的基线 FinFET 相比，当它在较低的电压下工作时——由于额外的铁电引起的变化。结果还表明，忽略工艺变化会导致高估 NC 给处理器频率改进带来的好处，因为需要更大的时序保护带来克服 NC-FinFET 的变化。