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Bandwidth-Enhanced Oversampling Successive Approximation Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer
IEEE Journal of Solid-State Circuits ( IF 5.4 ) Pub Date : 2020-09-01 , DOI: 10.1109/jssc.2020.3005811
Longjie Zhong , Jun Yang , Donglai Xu , Xinquan Lai

The bandwidth-enhanced oversampling successive approximation (BE-OSA) readout technique is proposed in this article to reduce the noise floor of the readout circuit for micro-electromechanical systems (MEMS) capacitive accelerometer while achieving high power efficiency in terms of the figure of merit (FoM). The open-loop structure has been widely used in MEMS capacitive accelerometer for the Internet of Things (IoT) applications due to its low power consumption. However, in the open-loop accelerometer, the capacitance variation in the sensing element is limited to the femto-farad level to overcome nonlinearity. As a result, the thermal noise from the parasitic capacitance becomes significant. The ability of the readout circuit to deal with thermal noise is determined by the front-end switched-capacitor capacitance-to-voltage convertor (SC CVC) rather than the back-end analog-to-digital converter (ADC). To reduce the noise floor, the traditional oversampling method increases the sampling frequency of SC CVC by increasing the transconductance of the amplifier, but this leads to low power efficiency. In this work, the BE-OSA technique provides a high power efficiency method as it increases the sampling frequency of SC CVC without increasing the transconductance of the amplifier. The SC CVC based on the BE-OSA technique is demonstrated in a readout circuit fabricated by a commercial 0.18- $\mu \text{m}$ Bipolar-CMOS-DMOS (BCD) process and tested with a femto-farad MEMS accelerometer. The measurement results show that compared with the readout circuit without using the BE-OSA technique, the readout circuit using BE-OSA reduces the noise floor from 2.5 to 0.9 aF/ $\surd $ Hz. Compared with other similar works, the proposed readout circuit achieves the best power efficiency in terms of both the absolute power efficiency ( $FoM_{2} =243$ fJ) among the switched-capacitor readout circuits and the relative power efficiency ( $FoM_{3} = 0.14$ ).

中文翻译:

低噪声高效率MEMS电容式加速度计的带宽增强过采样逐次逼近读出技术

本文提出了带宽增强过采样逐次逼近 (BE-OSA) 读出技术,以降低微机电系统 (MEMS) 电容式加速度计读出电路的本底噪声,同时在品质因数方面实现高功率效率(FoM)。由于其低功耗,开环结构已广泛应用于物联网 (IoT) 应用的 MEMS 电容式加速度计。然而,在开环加速度计中,传感元件中的电容变化被限制在飞法拉级别以克服非线性。结果,寄生电容的热噪声变得很大。读出电路处理热噪声的能力取决于前端开关电容器电容电压转换器 (SC CVC),而不是后端模数转换器 (ADC)。为了降低本底噪声,传统的过采样方法通过增加放大器的跨导来提高SC CVC的采样频率,但这会导致低功率效率。在这项工作中,BE-OSA 技术提供了一种高功率效率方法,因为它在不增加放大器跨导的情况下增加了 SC CVC 的采样频率。基于 BE-OSA 技术的 SC CVC 在由商用 0.18- 传统的过采样方法通过增加放大器的跨导来增加SC CVC的采样频率,但这会导致低功率效率。在这项工作中,BE-OSA 技术提供了一种高功率效率方法,因为它在不增加放大器跨导的情况下增加了 SC CVC 的采样频率。基于 BE-OSA 技术的 SC CVC 在由商用 0.18- 传统的过采样方法通过增加放大器的跨导来增加SC CVC的采样频率,但这会导致低功率效率。在这项工作中,BE-OSA 技术提供了一种高功率效率方法,因为它在不增加放大器跨导的情况下增加了 SC CVC 的采样频率。基于 BE-OSA 技术的 SC CVC 在由商用 0.18- $\mu \text{m}$ 双极-CMOS-DMOS (BCD) 工艺并使用飞法拉 MEMS 加速度计进行测试。测量结果表明,与未使用 BE-OSA 技术的读出电路相比,使用 BE-OSA 技术的读出电路将本底噪声从 2.5 降低至 0.9 aF/ $\surd $ 赫兹。与其他类似工作相比,所提出的读出电路在绝对功率效率( $FoM_{2} =243$ fJ) 之间的开关电容器读出电路和相对功率效率 ( $FoM_{3} = 0.14$ )。
更新日期:2020-09-01
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