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Low-Power Resistive Memory Integrated on III-V Vertical Nanowire MOSFETs on Silicon
IEEE Electron Device Letters ( IF 4.9 ) Pub Date : 2020-09-01 , DOI: 10.1109/led.2020.3013674
Mamidala Saketh Ram , Karl-Magnus Persson , Mattias Borg , Lars-Erik Wernersson

III-V vertical nanowire MOSFETs (VNW-FETs) have the potential to extend Moore’s law owing to their excellent material properties. To integrate highly scaled memory cells coupled with high performance selectors at minimal memory cell area, it is attractive to integrate low-power resistive random access memory (RRAM) cells directly on to III-V VNW-FETs. In this work, we report the experimental demonstration of successful RRAM integration with III-V VNW-FETs. The combined use of VNW-FET drain metal electrode and the RRAM bottom electrode reduces the process complexity and maintains material compatibility. The vertical nanowire geometry allows the RRAM cell area to be aggressively scaled down to $0.01~\mu ^{m2}$ enabling realization of dense memory (1T1R) cross-point arrays on silicon.

中文翻译:

集成在硅基 III-V 族垂直纳米线 MOSFET 上的低功耗电阻式存储器

III-V 族垂直纳米线 MOSFET (VNW-FET) 由于其出色的材料特性而具有扩展摩尔定律的潜力。为了以最小的存储单元面积集成与高性能选择器相结合的高度缩放的存储单元,将低功耗电阻随机存取存储器 (RRAM) 单元直接集成到 III-V VNW-FET 上是很有吸引力的。在这项工作中,我们报告了 RRAM 与 III-V VNW-FET 成功集成的实验演示。VNW-FET漏极金属电极和RRAM底部电极的结合使用降低了工艺复杂性并保持了材料兼容性。垂直纳米线几何形状允许 RRAM 单元面积积极缩小到 $0.01~\mu^{m2}$,从而能够在硅上实现密集存储器 (1T1R) 交叉点阵列。
更新日期:2020-09-01
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