In many Multi-Processor Systems-on-Chip (MPSoCs), traffic between cores is unbalanced. This motivates the use of an application-specific Network-on-Chip (NoC) that is customized and can provide a high performance at low cost in terms of power and area. However, finding an optimized application-specific NoC architecture is a challenging task due to the huge design space. This article proposes to apply machine learning approaches for this task. Using graph rewriting, the NoC Design Space Exploration (DSE) is modelled as a Markov Decision Process (MDP). Monte Carlo Tree Search (MCTS), a technique from reinforcement learning, is used as search heuristic. Our experimental results show that—with the same cost function and exploration budget—MCTS finds superior NoC architectures compared to Simulated Annealing (SA) and a Genetic Algorithm (GA). However, the NoC DSE process suffers from the high computation time due to expensive cycle-accurate SystemC simulations for latency estimation. This article therefore additionally proposes to replace latency simulation by fast latency estimation using a Recurrent Neural Network (RNN). The designed RNN is sufficiently general for latency estimation on arbitrary NoC architectures. Our experiments show that compared to SystemC simulation, the RNN-based latency estimation offers a similar speed-up as the widely used Queuing Theory (QT). Yet, in terms of estimation accuracy and fidelity, the RNN is superior to QT, especially for high-traffic scenarios. When replacing SystemC simulations with the RNN estimation, the obtained solution quality decreases only slightly, whereas it suffers significantly when QT is used.

中文翻译：

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用于特定应用 NoC 的高效设计空间探索的机器学习方法

在许多多处理器片上系统 (MPSoC) 中，内核之间的流量是不平衡的。这促使人们使用定制的特定应用片上网络 (NoC)，它可以在功耗和面积方面以低成本提供高性能。然而，由于巨大的设计空间，寻找优化的特定于应用程序的 NoC 架构是一项具有挑战性的任务。本文建议将机器学习方法应用于此任务。使用图形重写，NoC 设计空间探索 (DSE) 被建模为马尔可夫决策过程 (MDP)。蒙特卡洛树搜索 (MCTS) 是强化学习中的一种技术，被用作启发式搜索。我们的实验结果表明，在成本函数和探索预算相同的情况下，与模拟退火 (SA) 和遗传算法 (GA) 相比，MCTS 发现了更好的 NoC 架构。然而，由于用于延迟估计的昂贵的周期精确 SystemC 模拟，NoC DSE 过程的计算时间长。因此，本文还建议通过使用循环神经网络 (RNN) 的快速延迟估计来替代延迟模拟。设计的 RNN 对于任意 NoC 架构的延迟估计来说足够通用。我们的实验表明，与 SystemC 仿真相比，基于 RNN 的延迟估计提供了与广泛使用的排队理论 (QT) 类似的加速。然而，在估计精度和保真度方面，RNN 优于 QT，尤其是在高流量场景下。当用 RNN 估计替换 SystemC 模拟时，获得的解决方案质量仅略有下降，而使用 QT 时会受到显着影响。