A wide-band-gap (WBG) SiC/Al₄SiC₄ heterostructure transistor with a gate length of 5 μm is designed using a ternary carbide of Al₄SiC₄, and its performance is simulated by Silvaco Atlas. The simulations use a mixture of parameters obtained from ensemble Monte Carlo simulations, DFT calculations, and experimental data. The 5 μm gate length transistor is then laterally scaled to 2 and 1 μm gate length devices. The 5 μm gate length SiC/Al₄SiC₄ heterostructure transistor delivers a maximum drain current of 168 mA/mm, which increases to 244 mA/mm and 350 mA/mm for gate lengths of 2 and 1 μm, respectively. The device breakdown voltage is 59.0 V, which reduces to 31.0 V and to 18.0 V in the scaled 2 μm and the 1 μm gate length transistors, respectively. The scaled down 1 μm gate length device switches faster thanks to a higher transconductance of 65.1 mS/mm compared to only 1.69 mS/mm for the 5 μm gate length device. Finally, the subthreshold slope of the scaled devices is 197.3, 97.6, and 96.1 mV/dec for gate lengths of 5, 2, and 1 μm, respectively.

中文翻译：

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SiC / Al ₄ SiC _4基异质结构晶体管

使用Al ₄ SiC ₄三元碳化物设计了栅长为5μm的宽带隙SiC / Al ₄ SiC ₄异质结构晶体管，并通过Silvaco Atlas模拟了其性能。这些模拟使用了从整体Monte Carlo模拟，DFT计算和实验数据中获得的参数混合。然后将5μm栅极长度的晶体管横向缩放至2和1μm栅极长度的器件。5μm栅长SiC / Al ₄ SiC ₄异质结晶体管的最大漏极电流为168 mA / mm，对于2和1μm的栅极长度，分别增加到244 mA / mm和350 mA / mm。器件击穿电压为59.0 V，在按比例缩放的2μm和1μm栅极长度的晶体管中，该电压分别降至31.0 V和18.0V。缩小尺寸的1μm栅极长度器件的开关速度更快，这归功于65.1 mS / mm的跨导，而5μm栅极长度器件的跨导仅为1.69 mS / mm。最后，对于5、2和1μm的栅极长度，缩放后的器件的亚阈值斜率分别为197.3、97.6和96.1 mV / dec。