The interaction between cores and memory blocks, in multiprocessor chips and smart systems, has always been a concern as it affects network latency, memory capacity, and power consumption. A new 2.5-dimensional architecture has been introduced in which the communication between the processing elements and the memory blocks is provided through a layer called the interposer. If the core wants to connect to another, it uses the top layer, and if it wants to interact with the memory blocks, it uses the interposer layer. In a case that coherence traffic at the processing layer increases to the extent that congestion occurs, a part of this traffic may be transferred to the interposer network under a mechanism called load balancing. When coherence traffic is moved to the interposer layer, as an alternative way, this may interfere with memory traffic. This paper introduces a mechanism in which the aforementioned interference may be avoided by defining two different virtual channels and using multiple links which specifically determines which memory block is going to be accessed. Our method is based on the destination address to recognize which channel and link should be selected while using the interposer layer. The simulation results show that the proposed mechanism has improved by 32% and 14% latency compared to the traditional load-balancing and unbalanced mechanisms, respectively.

中文翻译：

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使用特定虚拟通道管理基于中介层的片上网络中的负载平衡数据流

在多处理器芯片和智能系统中，内核与内存块之间的交互一直受到关注，因为它会影响网络延迟，内存容量和功耗。引入了新的2.5维体系结构，其中处理元素与存储块之间的通信通过称为中介层的层提供。如果内核要连接到另一个内核，则使用顶层；如果内核要与内存块进行交互，则使用中介层。如果处理层的一致性流量增加到发生拥塞的程度，则可以在称为负载平衡的机制下将此流量的一部分传输到中介层网络。作为一种替代方式，将一致性流量移动到中介层时，这可能会干扰内存流量。本文介绍了一种机制，其中可以通过定义两个不同的虚拟通道并使用多个链接（具体确定要访问哪个存储块）来避免上述干扰。我们的方法基于目标地址，以识别在使用中介层时应选择哪个通道和链接。仿真结果表明，与传统的负载平衡和不平衡机制相比，该机制的延迟分别提高了32％和14％。我们的方法基于目标地址，以识别在使用中介层时应选择哪个通道和链接。仿真结果表明，与传统的负载平衡和不平衡机制相比，该机制的延迟分别提高了32％和14％。我们的方法基于目标地址，以识别在使用中介层时应选择哪个通道和链接。仿真结果表明，与传统的负载平衡和不平衡机制相比，该机制的延迟分别提高了32％和14％。