This paper presents a 10-bit ultra-low power least-significant bit first (LSB-first) successive approximation register analog-to-digital converter used in wearable electrocardiogram monitoring. Compared with the exsiting ones, the number of bitcycles taken in the proposed LSB-first scheme only relates to the difference between two adjacent samples and the capacitor array is reduced by 50%. Fabricated in 65 ​nm CMOS technology within a bio-sensor front-end circuit, the proposed LSB-first SAR ADC occupies an active area of 200 ​× ​450 ​μm², consumes 60.8 ​nW ​at 10 ​kHz sampling rate, and achieves 58.4 ​dB SNDR.

中文翻译：

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使用新颖的LSB优先逐次逼近的10位SAR ADC，以减少位周期

本文提出了一种用于可穿戴心电图监测的10位超低功耗最低有效位优先（LSB-first）逐次逼近寄存器模数转换器。与现有的相比，在建议的LSB优先方案中采用的比特周期数仅与两个相邻样本之间的差异有关，电容器阵列减少了50％。生物传感器的前端电路中在65纳米CMOS技术制造的，所提出的LSB优先SAR ADC占据的200×450微米的活性区域²，消耗60.8纳瓦以10kHz采样率，并达到58.4 dB SNDR。