The scaling of RESET current ( $I_{\mathrm{ RESET}}$ ) used for reamorphization in phase-change memory (PCM) devices has been a challenging task to meet the energy-efficient programming. The faithful prediction of $I_{\mathrm{ RESET}}$ of scaled-down devices demands realistic physical models in order to examine low-power, miniaturized device characteristics, and the potential of a highly scalable PCM technology. Therefore, modeling the intrinsic interface effects, thermal boundary resistance (TBR) at the GeSbTe (GST)–metal and GST–oxide interfaces, and electrical interface resistance (EIR) at the GST–metal interface of the nanoscale PCM device is necessary. In this paper, the impact of presence and absence of TBR and EIR on $I_{\mathrm{ RESET}}$ in a mushroom-type PCM device is investigated, and their usefulness on scaling is predicted for diminished devices. Reductions in $I_{\mathrm{ RESET}}$ , 32% in the case of 100 nm contact diameter (CD), 45% for the 40-nm CD and 73% for the 10-nm CD are achieved by taking into account of interface effects, and these results are validated with experimental results published elsewhere. The fitted model suggests $I_{\mathrm{ RESET}}$ scales down linearly with CD and necessitates for the combined effects of TBR and EIR to successfully follow the isotropic scaling in mushroom-type devices. Hence, our simulation results demonstrate the significance of TBR and EIR for a better optimization and a reliable prediction of $I_{\mathrm{ RESET}}$ for low-power programming of PCM devices toward enabling next generation high-speed, high-density nonvolatile memory applications.

中文翻译：

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热边界电阻对相变存储器件性能和缩放的影响

RESET 电流的缩放比例 ( $I_{\mathrm{ 重置}}$ ) 用于相变存储器 (PCM) 设备中的重晶化一直是满足节能编程的一项具有挑战性的任务。忠实的预测 $I_{\mathrm{ 重置}}$ 缩小设备的数量需要真实的物理模型，以检查低功耗、小型化设备的特性以及高度可扩展的 PCM 技术的潜力。因此，有必要对纳米级 PCM 器件的 GeSbTe (GST)-金属和 GST-氧化物界面处的固有界面效应、热边界电阻 (TBR) 以及 GST-金属界面处的界面电阻 (EIR) 进行建模。在本文中，存在和不存在 TBR 和 EIR 对 $I_{\mathrm{ 重置}}$ 在蘑菇型 PCM 设备中进行了研究，并预测了它们对缩小设备的缩放有用性。减少 $I_{\mathrm{ 重置}}$ , 在 100 nm 接触直径 (CD) 的情况下，32%、40-nm CD 为 45% 和 10-nm CD 为 73% 是通过考虑界面效应实现的，这些结果通过实验结果进行验证在别处发表。拟合模型表明 $I_{\mathrm{ 重置}}$ 随 CD 线性缩小，并且需要 TBR 和 EIR 的组合效应才能成功遵循蘑菇型器件中的各向同性缩放。因此，我们的模拟结果证明了 TBR 和 EIR 对于更好的优化和可靠预测的重要性 $I_{\mathrm{ 重置}}$ 用于 PCM 器件的低功耗编程，以实现下一代高速、高密度非易失性存储器应用。