With the scaling limitations and increasing leakage power of the existing charge-based memories, next-generation memory technologies to overcome the issues are in development. Among the various emerging memories, phase change memory (PCM) is considered as a promising candidate due to its scalability potential and negligible leakage power. For enhanced storage density, the multilevel cell (MLC) operation has been proposed for PCM. This, however, comes at cost of poor reliability, write energy increase and performance degradation. Unlike DRAM, the MLC PCM has a much higher soft error rate due to the resistance drift phenomenon. Error correction code (ECC) schemes can be utilized to improve the MLC PCM reliability, however, this would lead to a lower storage density and an increase in write energy and latency. The iterative programming required for the MLC PCM also degrades its energy efficiency and performance. This paper introduces a simple yet effective encoding scheme to mitigate the problems of the MLC PCM. By using a simple XOR-based encoding, the proposed architecture minimizes the most drift-prone state in the data. The method divides the original data into several encoding blocks and analyzes initial pattern frequencies for each 2-bit pattern. Based on the initial pattern frequencies, the inputs for the XOR encoding are selected that result in minimal frequency of the drift-prone state. This considerably enhances the MLC PCM reliability, leading to a high storage density with a reduced ECC overhead. The energy efficiency and performance are also improved due to reduction in iterative current pulses and ECC overhead. The simulation results show a reduction of about $10^{5}$ X in soft error rate. The improvements in energy efficiency and performance over the conventional 4-level cell (4LC) PCM are 11.5% and 31.9%, respectively.

中文翻译：

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用于 MLC PCM 存储密度、能源效率和性能增强的模式感知编码

随着现有基于电荷的存储器的缩放限制和不断增加的泄漏功率，解决这些问题的下一代存储器技术正在开发中。在各种新兴存储器中，相变存储器 (PCM) 因其可扩展性潜力和可忽略的泄漏功率而被认为是有前途的候选者。为了提高存储密度，已为 PCM 提出了多级单元 (MLC) 操作。然而，这是以可靠性差、写入能量增加和性能下降为代价的。与 DRAM 不同，由于电阻漂移现象，MLC PCM 具有更高的软错误率。纠错码 (ECC) 方案可用于提高 MLC PCM 的可靠性，但是，这会导致较低的存储密度以及写入能量和延迟的增加。MLC PCM 所需的迭代编程也会降低其能效和性能。本文介绍了一种简单而有效的编码方案来缓解 MLC PCM 的问题。通过使用简单的基于 XOR 的编码，所提出的架构最大限度地减少了数据中最容易漂移的状态。该方法将原始数据分成几个编码块，并分析每个 2 位模式的初始模式频率。根据初始模式频率，选择 XOR 编码的输入，以产生易于漂移的状态的最小频率。这大大提高了 MLC PCM 的可靠性，从而实现了高存储密度，同时降低了 ECC 开销。由于迭代电流脉冲和 ECC 开销的减少，能源效率和性能也得到了提高。仿真结果表明，软错误率降低了约 $10^{5}$X。与传统的 4 级电池 (4LC) PCM 相比，能效和性能分别提高了 11.5% 和 31.9%。