An area-efficient N-bit digital comparator with high operating speed and low-power dissipation is presented in this work. The proposed comparator structure consists of two separate modules. The first module is the comparison evaluation module (CEM) and the second module is the final module (FM). Independent from the input operand bitwidths, stages present in CEM involve the regular structure of repeated logic cells used for implementing parallel prefix tree structure. The FM validates the final comparison based on results obtained from the CEM. The presence of regular very large-scale integration topology in the proposed structure allows the analytical derivation of the area in terms of total number of transistors present in the design and total delay encountered in input-output flow as the function of input operand bitwidth. Spectre simulation results have been presented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology at 1 GHz. The main advantages of the proposed comparator are minimum input-output delay of 0.57 ns, minimum fan-out-of-4 delay of 9.5 ns and low-power dissipation of 1.03 mw as compared with existing comparators designed using 180 nm CMOS technology for 64 bit comparison.

中文翻译：

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高速和区域高效的可扩展 ñ位数字比较器

这项工作提出了一种具有高工作速度和低功耗的面积有效的N位数字比较器。拟议的比较器结构由两个独立的模块组成。第一个模块是比较评估模块（CEM），第二个模块是最终模块（FM）。与输入操作数的位宽无关，CEM中存在的阶段涉及用于实现并行前缀树结构的重复逻辑单元的规则结构。FM根据从CEM获得的结果验证最终比较。所提出的结构中规则的超大规模集成拓扑的存在允许根据设计中存在的晶体管总数和输入输出流中遇到的总延迟（作为输入操作数位宽的函数）来分析面积。使用0.18μm互补金属氧化物半导体（CMOS）技术在1 GHz处已提供了光谱模拟结果。与使用180 nm CMOS技术设计的现有比较器相比，拟议的比较器的主要优点是：最小输入输出延迟为0.57 ns，最小扇出4延迟为9.5 ns，低功耗为1.03 mw。位比较。