In this work, we propose valley-coupled spin-hall memories based on monolayer WSe2. The key features of the proposed memories are (a) the ability to switch magnets with perpendicular magnetic anisotropy and (b) an integrated gate that can modulate the charge/spin current ($I_C / I_S$) flow. The former attribute results in high energy efficiency (compared to the Giant-Spin Hall (GSH) effect-based devices with in-plane magnetic anisotropy magnets). The latter feature leads to a compact access-transistor-less memory array design. We experimentally measure the gate controllability of the current as well as the non-local resistance associated with valley-coupled spin-hall effect. Based on the measured data, we develop a simulation framework to propose and analyze single-ended and differential valley-coupled spin-hall effect based magnetic memories (VSH-MRAM and DVSH-MRAM, respectively). At the array level, the proposed VSH/DVSH-MRAMs achieve 50%/11% lower write time, 59%/67% lower write energy, 12%/30% lower read time and 35%/41% lower read energy at iso-sense margin, compared to single-ended/differential Giant-Spin Hall (GSH/DGSH)-MRAMs. System level evaluation in the context of general-purpose processor and intermittently-powered system shows up to 3.14X and 1.98X better energy efficiency for the proposed (D)VSH-MRAMs over (D)GSH-MRAMs respectively. Further, the differential sensing of the proposed DVSH-MRAM leads to natural and simultaneous in-memory computation of bit-wise AND and NOR logic functions. Using this feature, we design a computation-in-memory (CiM) architecture that performs Boolean logic and addition with a single array access. System analysis performed by integrating our DVSH-MRAM: CiM in the Nios II processor shows up to 2.57X total energy savings, compared to DGSH-MRAM: CiM.

中文翻译：

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具有 Compute-In-Memory 支持的 Valley-Coupled-Spintronic 非易失性存储器

在这项工作中，我们提出了基于单层 WSe2 的谷耦合自旋霍尔存储器。所提出的存储器的主要特征是 (a) 能够切换具有垂直磁各向异性的磁铁和 (b) 可以调节电荷/自旋电流 ($I_C / I_S$) 流的集成栅极。前一个属性导致高能效（与具有平面内磁各向异性磁铁的基于巨自旋霍尔 (GSH) 效应的设备相比）。后一特征导致紧凑的无存取晶体管存储器阵列设计。我们通过实验测量了电流的栅极可控性以及与谷耦合自旋霍尔效应相关的非局部电阻。根据实测数据，我们开发了一个仿真框架来提出和分析基于单端和差分谷耦合自旋霍尔效应的磁存储器（分别为 VSH-MRAM 和 DVSH-MRAM）。在阵列级别，所提出的 VSH/DVSH-MRAM 在 iso 下实现了 50%/11% 的写入时间降低、59%/67% 的写入能量、12%/30% 的读取时间和 35%/41% 的读取能量降低-sense 裕度，与单端/差分巨自旋霍尔 (GSH/DGSH)-MRAM 相比。在通用处理器和间歇供电系统背景下的系统级评估显示，所提出的 (D)VSH-MRAM 的能效分别比 (D)GSH-MRAM 高 3.14 倍和 1.98 倍。此外，所提出的 DVSH-MRAM 的差分感测导致按位 AND 和 NOR 逻辑函数的自然和同步内存计算。使用此功能，我们设计了一种内存计算 (CiM) 架构，该架构通过单个数组访问执行布尔逻辑和加法。通过在 Nios II 处理器中集成我们的 DVSH-MRAM: CiM 执行的系统分析显示，与 DGSH-MRAM: CiM 相比，总节能高达 2.57 倍。