In multi-processor system-on-chips, on-chip interconnection plays a significant role. The type of on-chip architecture being used in an application decides the performance of that application. Hence, a quick and versatile network-on-Chip (NoC) simulator, particularly for the larger designs, is essential to explore and find the best suitable NoC configuration for individual applications. An FPGA-based NoC simulation framework has been proposed in this work. The crossbar switch of the NoC router with buffers and five ports has been embedded in the wide multiplexers of the DSP48E1 slices. The distinctive feature of dynamic mode functionality of the DSP48E1 slices every clock cycle depending on the control signals of multiplexer plays a crucial role in incorporating the crossbar functionality. A substantial decrease in the configurable logic blocks (CLBs) utilization of NoC topologies on the FPGA has been observed by embedding the functionality of the crossbar on the DSP48E1 slices. Since there is a reduction in the use of CLB resources employing the crossbar based on DSP48E1, topologies of larger sizes can be simulated. $$6\times 6$$ 6 × 6 Mesh topology with the DSP crossbar implementation consumes 36% fewer lookup tables (LUTs) and 40% fewer flip flops than the Mesh topology with CLB-based crossbar implementation. 41% fewer LUTs and 23% fewer slices are consumed by the proposed work with respect to the state-of-the-art CONNECT NoC generation tool. Compared to DART, a reduction of 86% and 80% in LUTs and slices has been observed with respect to the proposed work. Hoplite-DSP implements the unidirectional Torus topology with no buffers considering the deflective routing algorithm. The proposed work targets Mesh-based topologies with buffers and bidirectional ports with XY and look-ahead routing algorithms.

中文翻译：

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利用硬模块的高效基于 FPGA 的片上网络仿真框架

在多处理器片上系统中，片上互连起着重要作用。应用程序中使用的片上架构类型决定了该应用程序的性能。因此，快速且多功能的片上网络 (NoC) 模拟器，尤其是对于大型设计，对于探索和找到适合各个应用的最佳 NoC 配置至关重要。在这项工作中已经提出了一个基于 FPGA 的 NoC 仿真框架。带有缓冲器和五个端口的 NoC 路由器的纵横开关已嵌入到 DSP48E1 片的宽多路复用器中。DSP48E1 动态模式功能的显着特点根据多路复用器的控制信号在每个时钟周期进行切片，这在整合交叉开关功能方面起着至关重要的作用。通过在 DSP48E1 Slice 上嵌入交叉开关的功能，已经观察到 FPGA 上 NoC 拓扑的可配置逻辑块 (CLB) 利用率显着降低。由于采用基于 DSP48E1 的交叉开关减少了 CLB 资源的使用，因此可以模拟更大尺寸的拓扑。$$6\times 6$$ 6 × 6 与采用基于 CLB 的交叉开关实现的网格拓扑相比，采用 DSP 交叉开关实现的网格拓扑减少了 36% 的查找表 (LUT) 和 40% 的触发器。与最先进的 CONNECT NoC 生成工具相关的拟议工作消耗的 LUT 减少了 41%，切片消耗减少了 23%。与 DART 相比，已观察到与拟议工作相关的 LUT 和切片减少了 86% 和 80%。考虑到偏转路由算法，Hoplite-DSP 实现了无缓冲器的单向环面拓扑。拟议的工作目标是基于 Mesh 的拓扑结构，带有缓冲区和双向端口，带有 XY 和前瞻路由算法。