Today’s systems on chip (SoCs) require a complex design and verification process. In early design stages, high-level debugging of the SoC functionality is feasible on TLM (Transaction-Level Modeling) descriptions. To ease debugging of such SoC’s models, Assertion-Based Verification (ABV) enables the runtime verification of temporal properties. In the last design stages, RTL (Register Transfer Level) descriptions of hardware blocks expose microarchitectural details. To gain confidence in the validity of system level properties after this TLM-to-RTL synthesis, transaction level assertions must be reverifiable on RTL models. To address that issue, we propose refinement rules for the automatic system level to signal level transformation of PSL assertions (Property Specification Language, IEEE standard 1850). We sketch the architecture of a prototype tool that automates this refinement, and we give some illustrative examples for a realistic use case.

当今的片上系统（SoC）需要复杂的设计和验证过程。在早期设计阶段，可以在TLM（事务级别建模）描述中对SoC功能进行高级调试。为了简化此类SoC模型的调试，基于声明的验证（ABV）启用了时间属性的运行时验证。在最后的设计阶段，硬件块的RTL（寄存器传输级别）描述公开了微体系结构的详细信息。为了在从TLM到RTL的综合之后获得对系统级别属性有效性的信心，必须在RTL模型上重新验证事务级别的断言。为了解决该问题，我们提出了自动系统级到PSL断言的信号级转换的改进规则（属性规范语言，IEEE标准1850）。