In this article, an improved target impedance concept directly correlating circuit output jitter with power distribution network (PDN) R-L-C parameters is proposed. A systematic procedure to develop the target impedance curves is formulated and developed for common CMOS buffer circuits. The relationship between output jitter and PDN R-L-C parameters is analytically derived by evaluating the time domain voltage ripple to jitter transfer relationship along with the relationship between time domain voltage ripple and PDN R-L-C parameters. Given the transient integrated circuit switching current and the jitter specification, multiple target impedance curves can be defined for a specific circuit. The jitter and PDN R-L-C analytical correlations are validated through HSPICE simulation. The application of the proposed target impedance concept with jitter specification is also demonstrated via simulation.

中文翻译：

---

具有抖动规范的改进目标阻抗概念

在本文中，提出了一种改进的目标阻抗概念，将电路输出抖动与配电网络 (PDN) RLC 参数直接相关。为常见的 CMOS 缓冲电路制定和开发了开发目标阻抗曲线的系统程序。通过评估时域电压纹波到抖动传递的关系以及时域电压纹波和 PDN RLC 参数之间的关系，分析得出输出抖动和 PDN RLC 参数之间的关系。给定瞬态集成电路开关电流和抖动规格，可以为特定电路定义多条目标阻抗曲线。抖动和 PDN RLC 分析相关性通过 HSPICE 仿真得到验证。