This paper presents an 8-channel energy-efficient analog front-end (AFE) for neural recording, with improvements in power supply rejection ratio (PSRR) and dynamic range. The input stage in the low noise amplifier (LNA) adopts low voltage supply (0.35 V) and current-reusing to achieve ultralow power. To maintain a high PSRR performance while using such a low-voltage supply, a replica-biasing scheme is proposed to generate a stable bias current for the input stage of the LNA despite large supply interference. By exploiting the signal characteristics in the tetrode recording, an averaged local field potential (A-LFP) servo loop is introduced to extend the dynamic range without consuming too much extra power and chip area. The A-LFP signal is generated by integrating the four-channel PGA outputs from the same tetrode. Furthermore, the outputs of the programmable gain amplifier (PGA) are level shifted to bias the input nodes of the amplifier through large pseudo resistors, thus increase the maximum output range without distortion under the low-voltage supply. The proof-of-concept prototype is fabricated in a 65 nm CMOS process. Each recording channel including an LNA and a PGA occupies 0.04 mm $^2$ and consumes 340 nW from the 0.35 V and 0.7 V supply. Each A-LFP servo loop, which is shared by four recording channels, occupies 0.04 mm $^2$ and consumes 190 nW. The maximum gain of the AFE is 54 dB, and the input-referred noise is 6.7 $\mu$ V over the passband from 0.5 Hz to 6.5 kHz. Measurement also shows that the 0.35 V replica-biasing input stage can tolerate a large interferer up to 200 mVpp with a PSRR of 74 dB, which has been improved to 110 dB with a silicon respin that shields critical wires in the layout.

中文翻译：

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340 nW /通道110 dB PSRR神经记录模拟前端，使用复制偏置LNA，电平转换器辅助的PGA和65 nm CMOS中的平均LFP伺服环路。

本文提出了一种用于神经记录的8通道节能模拟前端（AFE），并改善了电源抑制比（PSRR）和动态范围。低噪声放大器（LNA）的输入级采用低压电源（0.35 V）和电流重用，以实现超低功耗。为了在使用这样的低压电源时保持较高的PSRR性能，尽管电源干扰较大，但提出了一种复制偏置方案来为LNA的输入级生成稳定的偏置电流。通过利用四极杆记录中的信号特性，引入了平均局部场电势（A-LFP）伺服环路以扩展动态范围，而不会消耗过多的额外功率和芯片面积。A-LFP信号是通过对同一四极管的四通道PGA输出进行积分而生成的。此外，可编程增益放大器（PGA）的输出经过电平移位，以通过较大的伪电阻对放大器的输入节点进行偏置，从而增加了最大输出范围，并且在低压电源下不会失真。概念验证原型是在65 nm CMOS工艺中制造的。每个包括LNA和PGA的记录通道占用0.04 mm $ ^ 2 $并从0.35 V和0.7 V电源消耗340 nW。每个A-LFP伺服回路（由四个记录通道共享）占用0.04毫米 $ ^ 2 $并消耗190 nW。AFE的最大增益为54 dB，参考输入噪声为6.7$ \ mu $ 通带上的V从0.5 Hz到6.5 kHz。测量还表明，0.35 V复制偏置输入级可以承受高达200 mVpp的大干扰，其PSRR为74 dB，而通过硅树脂旋转销屏蔽了布局中的关键导线，该干扰已提高至110 dB。