This paper presents noise reduction and modified asynchronous logic regulation techniques used in successive approximation register (SAR) analog-to-digital converter (ADC). With a transconductance enhanced structure, noise reduction is provided in the dynamic comparator. The input referred noise of the proposed comparator is about 165μV rms at 60^∘C (typical corner). An enhanced-positive-feedback loop is introduced to reduce the regeneration delay of the comparator. In addition, a modified asynchronous logic regulation technique is exhibited, a clock with adaptable delay is driving the comparator in approximation phase. Consequently, the settling accuracy of DAC (Digital-to-Analog Converter) is enough and the conversion speed of SAR ADC is increased without any redundant cycles. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 4mW from 1.2V power supply with a SNDR>66.7dB and SFDR>82.1dB. The proposed ADC core occupies an active area of 0.048mm², and the corresponding FoM is 27.2fJ/conversion-step at Nyquist rate.

中文翻译：

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具有改进的异步逻辑调节技术的降噪 12 位 125MSPS SAR ADC

本文介绍了在逐次逼近寄存器 (SAR) 模数转换器 (ADC) 中使用的降噪和改进的异步逻辑调节技术。采用跨导增强结构，动态比较器提供降噪功能。建议比较器的输入参考噪声约为 165μ60 ^∘ C 时的 V rms（典型拐角）。引入增强的正反馈环路以减少比较器的再生延迟。此外，还展示了一种改进的异步逻辑调节技术，具有自适应延迟的时钟在逼近阶段驱动比较器。因此，DAC（数模转换器）的建立精度足够，SAR ADC的转换速度提高，没有任何冗余周期。为了演示所提出的技术，SAR ADC 的设计采用 65-nm CMOS 技术制造，消耗 4毫瓦从 1.2V 电源与信噪比>66.7分贝和小号FDR>82.1D b。提议的 ADC 内核占用 0.048 的有效面积mm ²，对应的 FoM 为 27.2奈奎斯特速率下的 fJ/转换步长。