It has been shown that threading dislocations may be removed from patterned mismatched heteroepitaxial layers through a process of dislocation sidewall gettering (DSG), also known as patterned heteroepitaxial processing (PHeP). This gettering approach involves the glide of dislocations toward sidewalls, where they become trapped by image forces. Simple quantitative models have been developed for DSG, but they fail to explain why only partial removal of dislocations was observed in ZnSSe/GaAs (001) whereas complete removal has been achieved in ZnSe/GaAs (001) with higher lattice mismatch. Until now this phenomenon has been qualitatively explained by the presence of sessile dislocations. Here we present a quantitative model for pinning interactions and show that these interactions can limit the growth of misfit dislocation segments and thereby reduce the effectiveness of DSG in ZnS_ySe_1-y/GaAs (001) relative to ZnSe/GaAs (001).

已经显示，可以通过位错侧壁吸气（DSG）工艺（也称为图案化异质外延加工（PHeP））从图案化的失配异质外延层中去除螺纹位错。这种吸气方法涉及位错向侧壁的滑行，这些位错被图像力困住。已经为DSG开发了简单的定量模型，但是它们无法解释为什么在ZnSSe / GaAs（001）中仅观察到位错的部分去除，而在具有更高晶格失配的ZnSe / GaAs（001）中实现了完全去除。迄今为止，无柄位错的存在已定性地解释了这种现象。相对于ZnSe / GaAs（001）的_y Se _1-y / GaAs（001）。