In this study, we propose a SPICE model of p‐channel silicon tunneling field‐effect transistors (TFETs) for logic applications. To verify our model, electrical characteristics of fabricated p‐TFETs are calibrated by utilizing TCAD and SPICE simulations. We simulate various logic gates, such as complementary TFET (c‐TFET) inverters, c‐TFET NAND gates, and c‐TFET NOR gates using our TFET model. Our simulation shows that a c‐TFET inverter can be operated at V_DD as low as 0.3 V and that c‐TFET logic gates based on our model can operate ~1000 times higher frequency than conventional TFET logic gates.

中文翻译：

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用于逻辑应用的p沟道硅隧穿场效应晶体管的SPICE模型

在这项研究中，我们提出了用于逻辑应用的p沟道硅隧道场效应晶体管（TFET）的SPICE模型。为了验证我们的模型，通过利用TCAD和SPICE仿真来校准制造的p- TFET的电特性。我们使用TFET模型模拟各种逻辑门，例如互补TFET （c- TFET）反相器，c- TFET NAND门和c- TFET NOR门。我们的仿真表明，一个c- TFET反相器可以在低至0.3V的V _DD下工作，并且基于我们模型的c- TFET逻辑门的工作频率比传统TFET逻辑门高约1000倍。