High‐level synthesis (HLS), which automatically synthesizes a register‐transfer level (RTL) circuit from a behavioral description written in a high‐level programming language such as C/C++, is becoming a more popular technique for improving design productivity. In general, HLS tools often generate a circuit with a larger area than those of hand‐designed ones. One reason for this issue is that HLS tools often generate multiple instances of the same module from a function. To eliminate such a redundancy in circuit area in HLS, HLS tools are capable of sharing modules. Function‐level module sharing at a behavioral description written in a high‐level programming language may promote function reuse to increase effectiveness and reduce circuit area. In this paper, we present two HLS techniques for module sharing at the function level.

中文翻译：

---

高级综合中的功能级模块共享技术

高级合成（HLS）通过使用C / C ++等高级编程语言编写的行为描述自动合成寄存器传输级（RTL）电路，正在成为一种提高设计生产率的流行技术。通常，HLS工具生成的电路通常比手工设计的电路要大。出现此问题的原因之一是，HLS工具通常会从一个函数生成同一模块的多个实例。为了消除HLS中电路区域的这种冗余，HLS工具能够共享模块。以高级编程语言编写的行为描述中的功能级模块共享可以促进功能复用，从而提高有效性并减小电路面积。在本文中，我们介绍了两种在功能级别共享模块的HLS技术。