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FPGA implementation of an optimized A5/3 encryption algorithm
Microprocessors and Microsystems ( IF 2.6 ) Pub Date : 2020-08-03 , DOI: 10.1016/j.micpro.2020.103212
Mahdi Madani , Camel Tanougast

The radio link connecting users to network services is one of the most sensitive parts of mobile networks. This wireless channel is not protected physically to prevent unauthorized access to the carried information. Therefore, network providers use a security mechanism mainly based on cryptographic algorithms. For example, data protection (confidentiality) in the second and third generations of mobile networks is ensured using the A5/3 encryption algorithm (f8 function) standardized by the Third Generation Partnership Project (3GPP). In this work, we defined two main objectives for obtaining an optimized architecture of the A5/3 algorithm. The first one focuses on the optimization of the algorithm’s kernel (the KASUMI block cipher) by simplifying its internal architecture. The second one aims at the optimization of the A5/3 algorithm using a single block of the simplified KASUMI, unlike the standard A5/3 algorithm based on five blocks of the basic KASUMI. As a result, good performance has been achieved by considering the tradeoff between high throughput and required hardware logic resources compared to previous works. The proposed architecture was implemented on several Xilinx Virtex Field Programmable Gate Arrays (FPGA) technology devices. The synthesis results obtained after place and route have demonstrated the feasibility and efficiency of our solution. This promising technique can be applied to provide real-time data protection on embedded applications of mobile networks.



中文翻译:

优化的A5 / 3加密算法的FPGA实现

将用户连接到网络服务的无线电链路是移动网络最敏感的部分之一。此无线通道没有受到物理保护,以防止未经授权访问所携带的信息。因此,网络提供商使用主要基于密码算法的安全机制。例如,使用第三代合作伙伴计划(3GPP)标准化的A5 / 3加密算法(f8功能)来确保第二代和第三代移动网络中的数据保护(机密性)。在这项工作中,我们定义了两个主要目标,以获得A5 / 3算法的优化架构。第一个重点是通过简化算法的内部架构来优化算法的内核(KASUMI块密码)。第二个目标是使用简化的KASUMI的单个块来优化A5 / 3算法,这与基于基本KASUMI的五个块的标准A5 / 3算法不同。结果,与以前的工作相比,通过考虑高吞吐量和所需的硬件逻辑资源之间的折衷,已经获得了良好的性能。所提议的架构是在多个Xilinx Virtex现场可编程门阵列(FPGA)技术设备上实现的。布局布线后得到的综合结果证明了我们解决方案的可行性和有效性。这种有前途的技术可以应用于在移动网络的嵌入式应用程序上提供实时数据保护。通过与以前的工作相比,在高吞吐量和所需的硬件逻辑资源之间进行权衡,已经获得了良好的性能。所提议的架构是在多个Xilinx Virtex现场可编程门阵列(FPGA)技术设备上实现的。布局布线后得到的综合结果证明了我们解决方案的可行性和有效性。这种有前途的技术可以应用于在移动网络的嵌入式应用程序上提供实时数据保护。通过与以前的工作相比,在高吞吐量和所需的硬件逻辑资源之间进行权衡,已经获得了良好的性能。所提议的架构是在多个Xilinx Virtex现场可编程门阵列(FPGA)技术设备上实现的。布局布线后得到的综合结果证明了我们解决方案的可行性和有效性。这种有前途的技术可以应用于在移动网络的嵌入式应用程序上提供实时数据保护。布局布线后得到的综合结果证明了我们解决方案的可行性和有效性。这种有前途的技术可以应用于在移动网络的嵌入式应用程序上提供实时数据保护。布局布线后得到的综合结果证明了我们解决方案的可行性和有效性。这种有前途的技术可以应用于在移动网络的嵌入式应用程序上提供实时数据保护。

更新日期:2020-08-03
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