Among instances when the data and image security in resource constrained environment (smart devices and the like) are to be taken into consideration, lightweight encryption algorithms accede in popularity and are deemed of to be of great merit. In devices as those of the sort mentioned, reducing both power consumption and gate count is always a prime concern. LEA, therefore, triumphs on merit, owing to its low consumption levels of hardware resources, which itself is a result of the adaption of simple modular addition, bitwise rotation and bitwise XOR (ARX) operation instead of the relatively more complex S-box technique. The algorithm in question supports keys of varying sizes three, to be precise: 128, 192 and 256-bit for the intent of providing three levels of image and data security. The hardware implementation of the LEA algorithm for the varying key sizes as mentioned above share significant kinship and hardware resources. This paper puts forward the proposition regarding a high speed low area unified architecture for LEA algorithm for three different sizes of key. The individual hardware implementations of the three key sizes tend to consume more hardware resources than those involved in the proposed unified architecture. The pipelined implementation of the proposed design improves operating frequency to a significant degree, with a little increase in the hardware costs. The design proposed in this paper notably supports three varying tile sizes, i.e. 256$\times 256,128\times 128,64\times$64, of an input image. As resolution of an input image may not necessarily be an integer multiple of the size of tile, smaller tile sizes at the image boundary can also be handled by the same architecture. The design hereby proposed has been implemented on both UMC ASIC 0.09-$\mathrm{\mu }\mathrm{m}$ and XC5VLX330T FPGA platforms and achieved maximum operating frequencies of 740 MHz and 292 MHz respectively. As its increasingly evident on account of the FPGA implementation outcomes, the proposed unified architecture results in vastly improved levels of operating frequency (34%, 33% and 131%) as opposed to the individually available LEA architectures (corresponding to three different key sizes: 128, 192 and 256-bit, respectively). Proposed architecture shows 28%, 35% and 45% increment in the hardware resources with respect to available LEA architectures with single key. The incorporation of the unified key generation technique and pipeline implementation of the algorithm are the main reasons for the more hardware utilization.

在考虑资源受限环境（智能设备等）中的数据和图像安全性的情况下，轻量级加密算法越来越受欢迎，并被认为具有很大的优点。在上述类型的设备中，降低功耗和门数始终是首要考虑因素。因此，LEA由于其硬件资源的低消耗而取得了优异的成绩，这本身就是采用简单的模块化加法，按位旋转和按位XOR（ARX）操作而不是相对较复杂的S-box技术的结果。所讨论的算法支持三种不同大小的密钥，准确地说是：128、192和256位，以提供三个级别的图像和数据安全性。如上所述，用于各种密钥大小的LEA算法的硬件实现共享大量的亲属关系和硬件资源。针对三种不同大小的密钥，提出了一种针对LEA算法的高速低面积统一架构的主张。与所提议的统一体系结构所涉及的硬件实现方式相比，三个密钥大小的各个硬件实现方案往往会消耗更多的硬件资源。拟议设计的流水线实施大大提高了工作频率，而硬件成本却有所增加。本文提出的设计特别支持三种不同的图块大小，即256 针对三种不同大小的密钥，提出了一种针对LEA算法的高速低面积统一架构的主张。与所提议的统一体系结构所涉及的硬件实现方式相比，三个密钥大小的各个硬件实现方案往往会消耗更多的硬件资源。拟议设计的流水线实施大大提高了工作频率，而硬件成本却有所增加。本文提出的设计特别支持三种不同的图块大小，即256 针对三种不同大小的密钥，提出了一种针对LEA算法的高速低面积统一架构的主张。与所提议的统一体系结构所涉及的硬件实现方式相比，三个密钥大小的各个硬件实现方案往往会消耗更多的硬件资源。拟议设计的流水线实施大大提高了工作频率，而硬件成本却有所增加。本文提出的设计特别支持三种不同的图块大小，即256 拟议设计的流水线实施大大提高了工作频率，而硬件成本却有所增加。本文提出的设计特别支持三种不同的图块大小，即256 拟议设计的流水线实施大大提高了工作频率，而硬件成本却有所增加。本文提出的设计特别支持三种不同的图块大小，即256$\times 256，128\times 128，64\times$输入图像的64个。由于输入图像的分辨率不一定是图块大小的整数倍，因此图像边界处的图块大小也可以由相同的体系结构处理。特此提议的设计已在UMC ASIC 0.09-上实现$\mathrm{\mu }\mathrm{米}$和XC5VLX330T FPGA平台，分别达到740 MHz和292 MHz的最大工作频率。由于其在FPGA实施成果上的日益明显，拟议的统一架构与单独使用的LEA架构（对应于三种不同的密钥大小）相比，极大地提高了工作频率水平（分别为34％，33％和131％）： 128、192和256位）。相对于具有单个密钥的可用LEA架构，建议的架构显示硬件资源增加了28％，35％和45％。统一密钥生成技术的结合以及算法的流水线实现是硬件利用率更高的主要原因。