A wide tuning range, low phase noise oscillator with 3 stage differential configuration is presented. GPDK 45 nm CMOS Technology is selected for the design and simulation of the proposed circuit, under power supply impediment of 1.1 V. Proposed delay cell features ultra wide tuning range as it utilizes dual control voltages ($V_{c1}$ and $V_{c2}$), enabling large current to flow in the circuit. As frequency of oscillation has linear proportionality with the bias current, this oscillator generates frequencies from 534 MHz to 18.56 GHz. The proposed circuit occupies chip area of $102.87\mathrm{\mu }$m${}^2$. This circuit offers power consumption of 1.13 mWatt and phase noise of $-108.61$ dBc/Hz (10 MHz offset frequency) at 5.82 GHz oscillation frequency. Performance of the proposed circuit is evaluated on various temperature, supply voltage and process corners. Total Harmonic Distortion (THD) profile is also measured through simulation. Because of wide frequency spectrum, low phase noise, small area and low power budget, proposed circuit can be utilized in various power electronic applications, medical equipments, communication and navigation systems.

提出了具有三级差分配置的宽调谐范围，低相位噪声振荡器。选择GPDK 45 nm CMOS技术，用于在1.1 V的电源阻抗下设计和仿真拟议的电路。拟议的延迟单元具有超宽的调谐范围，因为它利用了双控制电压（$V_{C\mathrm{1个}}$ 和 $V_{C2}$），使大电流流入电路。由于振荡频率与偏置电流成线性比例关系，因此该振荡器会产生534 MHz至18.56 GHz的频率。拟议的电路占用芯片面积$102。87\mathrm{\mu }$米${}^2$。该电路的功耗为1.13 mWatt，相位噪声为$-108。61$ 在5.82 GHz振荡频率下为dBc / Hz（10 MHz偏移频率）。拟议电路的性能在各种温度，电源电压和工艺拐角处进行评估。总谐波失真（THD）曲线也可以通过仿真来测量。由于频谱宽，相位噪声低，面积小和功率预算低，所提出的电路可以用于各种电力电子应用，医疗设备，通信和导航系统。