Existing architectures for the median filter are based on sorting algorithm where comparators are used in serial. This paper proposes a new high-speed architecture of two dimensional (2-D) median filter where compare and select modules are used in parallel to sort the incoming numbers. The hardware implementation results show that the proposed architecture (PA) operates at 26% and 34% higher frequency in Virtex 4 and Virtex 7 FPGA device, respectively, in comparison with the architectures reported. The PA is synthesized using the RTL Compiler of Cadence along with Faraday 180 nm standard cell library. The maximum operating frequency of the PA is 1.06 GHz with a total gate count of 917. The complete chip layout has been done using the SoC encounter tool. The area of the final chip is 0.13928 mm\(^2\) with a power consumption of 0.168 mW analysed using prime-power.

中值滤波器的现有架构基于排序算法，其中比较器串行使用。本文提出了一种新型的二维（2-D）中值滤波器高速架构，其中并行使用比较和选择模块对传入的数字进行排序。硬件实现结果表明，与所报告的架构相比，该架构（PA）在Virtex 4和Virtex 7 FPGA器件中的工作频率分别高出26％和34％。使用Cadence的RTL编译器以及法拉第180 nm标准细胞文库合成PA。PA的最大工作频率为1.06 GHz，总门数为917。完整的芯片布局已使用SoC遭遇工具完成。最终芯片的面积为0.13928毫米\（^ 2 \） 使用原功率分析得出的功耗为0.168 mW。