Sādhanā ( IF 0.849 ) Pub Date : 2020-08-01 , DOI: 10.1007/s12046-020-01431-0 Vasudeva Bevara, Pradyut Kumar Sanki
Existing architectures for the median filter are based on sorting algorithm where comparators are used in serial. This paper proposes a new high-speed architecture of two dimensional (2-D) median filter where compare and select modules are used in parallel to sort the incoming numbers. The hardware implementation results show that the proposed architecture (PA) operates at 26% and 34% higher frequency in Virtex 4 and Virtex 7 FPGA device, respectively, in comparison with the architectures reported. The PA is synthesized using the RTL Compiler of Cadence along with Faraday 180 nm standard cell library. The maximum operating frequency of the PA is 1.06 GHz with a total gate count of 917. The complete chip layout has been done using the SoC encounter tool. The area of the final chip is 0.13928 mm\(^2\) with a power consumption of 0.168 mW analysed using prime-power.