Networks-on-Chip (NoCs) used in commercial many-core processors typically incorporate priority arbitration. Moreover, they experience bursty traffic due to application workloads. However, most state-of-the-art NoC analytical performance analysis techniques assume fair arbitration and simple traffic models. To address these limitations, we propose an analytical modeling technique for priority-aware NoCs under bursty traffic. Experimental evaluations with synthetic and bursty traffic show that the proposed approach has less than 10% modeling error with respect to cycle-accurate NoC simulator.

中文翻译：

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优先仲裁和突发流量下 NoC 的分析性能建模

商用众核处理器中使用的片上网络 (NoC) 通常包含优先级仲裁。此外，由于应用程序工作负载，他们会遇到突发流量。然而，大多数最先进的 NoC 分析性能分析技术都假设公平仲裁和简单的流量模型。为了解决这些限制，我们为突发流量下的优先级感知 NoC 提出了一种分析建模技术。对合成和突发流量的实验评估表明，相对于周期精确的 NoC 模拟器，所提出的方法具有小于 10% 的建模误差。