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Fast Multibit Decision Polar Decoder for Successive-Cancellation List Decoding
Journal of Signal Processing Systems ( IF 1.8 ) Pub Date : 2020-07-28 , DOI: 10.1007/s11265-020-01570-x
Seo Lin Jeong , Jung Hyun Bae , Myung Hoon Sunwoo

Successive-cancellation list (SCL) decoding for polar codes has the disadvantage of high latency owing to serial operations. To improve the latency, several algorithms with additional circuits have been proposed, but the area becomes larger. This paper proposes a fast multibit decision method having-high area efficiency based on the SCL decoding algorithm. First, multiple bits can be determined to reduce clock cycles using new nodes represented by the information bits and frozen bits. We propose the new nodes called the combined nodes and the other node in this paper. The combined nodes that combine redundant operations of the fast-simplified SC (fast-SSC) algorithm can increase area efficiency. The other node with bit patterns other than the node types of the fast-SSC algorithm performs an 8-bit multibit decision to reduce the number of decoding cycles. Latency is further reduced by applying a sphere decoding method to the other node. In addition, a sorter is proposed to reduce the critical path delay. As a large number of path metrics causes sorter delays, the proposed sorter can achieve high throughput with the small area. The proposed (1024, 512) SCL decoder showed negligible performance degradation in the simulation using Matlab and was synthesized using 65 nm CMOS technology. The proposed decoder achieves about 1.3Gbps with the small area. As a result, the area-throughput efficiency is at least 1.4 times higher than the state-of-the-art works over 1 Gbps.



中文翻译:

快速多比特决策极地解码器,用于连续取消列表解码

极性代码的连续取消列表(SCL)解码由于串行操作而具有高延迟的缺点。为了改善等待时间,已经提出了几种带有附加电路的算法,但是面积变大了。提出了一种基于SCL解码算法的区域效率高的快速多比特决策方法。首先,可以确定多个位,以使用信息位和冻结位表示的新节点来减少时钟周期。在本文中,我们提出了新节点,称为合并节点和另一个节点。结合了快速简化SC(fast-SSC)算法的冗余操作的组合节点可以提高区域效率。具有快速SSC算法的节点类型以外的其他位模式的其他节点将执行8位多位判决,以减少解码周期数。通过将球面解码方法应用于其他节点,可以进一步减少延迟。另外,提出了一种分选机以减少关键路径延迟。由于大量的路径度量会导致分拣器延迟,因此建议的分拣器可以在较小的面积上实现高吞吐量。所提出的(1024,512)SCL解码器在使用Matlab进行的仿真中显示出可忽略的性能下降,并且使用65 提出的分拣机可以在较小的面积上实现高吞吐量。所提出的(1024,512)SCL解码器在使用Matlab进行的仿真中显示出可忽略的性能下降,并且使用65 提出的分拣机可以在较小的面积上实现高吞吐量。所提出的(1024,512)SCL解码器在使用Matlab进行的仿真中显示出可忽略的性能下降,并且使用65 nm CMOS技术。所提出的解码器以小面积实现约1.3Gbps。结果,面积吞吐量效率至少是1 Gbps以上的最新技术的1.4倍。

更新日期:2020-07-28
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