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A Systematic Investigation of State-of-the-Art SystemC Verification
Journal of Circuits, Systems and Computers ( IF 1.5 ) Pub Date : 2020-03-17 , DOI: 10.1142/s0218126620300135
Bin Lin 1 , Fei Xie 1
Affiliation  

The growing complexity of System-on-a-Chips (SoCs) and rapidly decreasing time-to-market have pushed the design abstraction to the electronic system level in order to increase design productivity. SystemC is a widely used electronic system level modeling language that enables quick prototyping and early verification in the SoC design process. The functional correctness of SystemC designs is often one of the greatest concerns in the SoC design process, since undetected design errors may propagate to low-level implementations or even final silicon products, which are costly to fix. However, SystemC verification is a challenging task due to its complex language features such as object-oriented constructs, hardware-oriented data types and concurrency. A variety of approaches have been proposed for SystemC verification in the past two decades. This work systematically investigates the state-of-the-art SystemC verification approaches by discussing their methodologies, advantages, and limitations, as well as presenting comparison among various approaches.

中文翻译:

最先进的 SystemC 验证的系统研究

系统级芯片 (SoC) 的日益复杂性和快速缩短的上市时间已将设计抽象推向电子系统级别,以提高设计生产力。SystemC 是一种广泛使用的电子系统级建模语言,可在 SoC 设计过程中实现快速原型设计和早期验证。SystemC 设计的功能正确性通常是 SoC 设计过程中最关心的问题之一,因为未检测到的设计错误可能会传播到低级实现甚至最终的硅产品,而这些产品的修复成本很高。然而,SystemC 验证是一项具有挑战性的任务,因为它具有复杂的语言特性,例如面向对象的构造、面向硬件的数据类型和并发性。在过去的二十年中,已经提出了各种用于 SystemC 验证的方法。
更新日期:2020-03-17
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