This paper presents the debug process of a 28[Formula: see text]GHz low noise amplifier (LNA) circuit layout. This study is guided utilizing an electromagnetic (EM) simulation program where inductive coupling, the parasitics of dc voltage line and ground line are extracted and simulated, their impacts on LNA performance are also quantitatively characterized. For validation, the circuit was designed and fabricated using GF8HP 0.13[Formula: see text]um SiGe BiCMOS process. The measurement shows that the gain S21 is 23.22[Formula: see text]dB, S11 and S22 are [Formula: see text] and [Formula: see text][Formula: see text]dB, respectively, and the noise figure is 4.26[Formula: see text]dB. The power consumption is 14.25[Formula: see text]mW, the chip area including pads is 540[Formula: see text][Formula: see text][Formula: see text]um.

中文翻译：

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通过电磁分析进行 28 GHz LNA 电路布局调试

本文介绍了 28[公式：见正文]GHz 低噪声放大器 (LNA) 电路布局的调试过程。本研究使用电磁 (EM) 仿真程序进行指导，在该程序中提取和仿真电感耦合、直流电压线和地线的寄生效应，还定量表征了它们对 LNA 性能的影响。为了验证，该电路是使用 GF8HP 0.13[公式：见正文]um SiGe BiCMOS 工艺设计和制造的。实测增益S21为23.22[公式：见文]dB，S11和S22分别为[公式：见文]和[公式：见文][公式：见文]dB，噪声系数为4.26 [公式：见正文]dB。功耗为14.25[公式：见文]mW，包括焊盘在内的芯片面积为540[公式：见文][公式：见文][公式：见文]um。