Proposed work presents an OR-XNOR-based thermal-aware synthesis approach to reduce peak temperature by eliminating local hotspots within a densely packed integrated circuit. Tremendous increase in package density at sub-nanometer technology leads to high power-density that generates high temperature and creates hotspots. A nonexhaustive meta-heuristic algorithm named nondominated sorting genetic algorithm-II (NSGA-II) has been employed for selecting suitable input polarity of mixed polarity dual Reed–Muller (MPDRM) expansion function to reduce the power-density. A parallel tabular technique is used for input polarity conversion from Product-of-Sum (POS) to MPDRM function. Without performance degradation, the proposed MPDRM approach shows more than 50% improvement in the area and power savings and around 6% peak temperature reduction for the MCNC benchmark circuits than that of earlier literature at the logic level. Algorithmic optimized circuit decompositions are implemented in physical design domain using CADENCE INNOVUS and HotSpot tool and silicon area, power consumption and absolute temperature are reported to validate the proposed technique.

中文翻译：

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使用并行表格技术的基于 NSGA-II 的热感知混合极性双 Reed-Muller 网络合成

提议的工作提出了一种基于 OR-XNOR 的热感知合成方法，通过消除密集封装集成电路中的局部热点来降低峰值温度。亚纳米技术封装密度的巨大增加导致产生高温并产生热点的高功率密度。一种非穷举的元启发式算法称为非支配排序遗传算法-II (NSGA-II) 已被用于选择混合极性双 Reed-Muller (MPDRM) 扩展函数的合适输入极性以降低功率密度。并行表格技术用于从和积 (POS) 到 MPDRM 函数的输入极性转换。在没有性能下降的情况下，所提出的 MPDRM 方法显示出 MCNC 基准电路的面积和功耗节省超过 50%，峰值温度降低了约 6%，与早期文献在逻辑级别上的相比。使用 CADENCE INNOVUS 和 HotSpot 工具在物理设计域中实现了算法优化电路分解，并报告了硅面积、功耗和绝对温度以验证所提出的技术。