This paper explores the design and analysis of 20[Formula: see text]nm tunnel transistor-based Exclusive-OR (Ex-OR) gates and half-adder cells with circuit interaction (co-design) approach for energy efficient and reliable computing architectures at scaled supply voltages (50–300[Formula: see text]mV). TFETs have attracted much attention recently for energy efficient system designs. The circuit interaction is made possible for designing more consistent functional architectures at the minimum power supply of 50–300[Formula: see text]mV. Using this technique, the core computational blocks of basic adder blocks and Ex-OR gates are designed with TFET as a fundamental device and the whole design procedure is elaborated in this paper. The primary classifications of Tunnel FETs, viz. Homo-junction TFET (HoJn TFET) and Hetero-junction TFETs (HeJn TFET) are investigated thoroughly under different constraints specifically at the device configurations. By considering the above-mentioned subtypes of TFETs, three variants of Ex-OR primitive gates are modeled and are named with respect to the use of transistors as static complementary TFET-12T (SC12T), Transmission Gate logic-8T (TG8T) and Improved Transmission Gate logic-6T (ITG6T) Ex-OR gate designs. The benchmarking of the proposed gates is done using double-gate Si FinFET at 20[Formula: see text]nm technology. Amongst all the three proposed Ex-OR designs of SC12T, TG8T and ITG6T in addition to that of LVT and HVT FinFET/CMOS, only ITG6T is the designer’s choice by offering the minimum power consumption as well as high energy, improved choice compared to the other two styles of designs and also when robustness and reliability are taken into account, SC12T and TG8T designs are not providing the full swing of outputs. The minute glitch with that of ITG6T designs is a lesser reliability feature and for this the best alternative is TFET TG8T by providing suppressed over shoots and enhanced transition speed. From the performed multi simulations under different critical conditions and at supply voltage of 100[Formula: see text]mV, it is being demonstrated that the energy efficient circuit option is the SC12T and ITG6T Ex-OR designs which are validated with the steep slope characteristics of TFET’s and also these two designs offer reliability advantage. The major restrictions from the energy efficiency issues are eliminated and disclosed in the HoJn TFETs and HeJn TFET by using circuit co-design methodology and TFETs steep slope characteristics.

中文翻译：

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用于节能计算的基于隧道晶体管的异或门的设备-电路交互和性能基准测试

本文探讨了基于 20[公式：见正文]nm 隧道晶体管的异或 (Ex-OR) 门和半加法器单元的设计和分析，以及电路交互（协同设计）方法，以实现高能效和可靠的计算架构在缩放的电源电压（50–300[公式：见文本]mV）。TFET 最近在节能系统设计方面引起了广泛关注。电路交互使设计更一致的功能架构成为可能，最小电源为 50–300 [公式：见正文]mV。使用这种技术，基本加法器块和异或门的核心计算块以TFET为基础器件进行设计，并在本文中详细阐述了整个设计过程。隧道 FET 的主要分类，即。同质结 TFET (HoJn TFET) 和异质结 TFET (HeJn TFET) 在不同的约束条件下进行了彻底的研究，特别是在器件配置方面。通过考虑上述 TFET 的子类型，对 Ex-OR 原始门的三种变体进行建模，并根据晶体管的使用命名为静态互补 TFET-12T (SC12T)、传输门逻辑-8T (TG8T) 和改进型传输门逻辑 6T (ITG6T) 异或门设计。所提出的栅极的基准测试是使用 20[公式：见文本]nm 技术的双栅极 Si FinFET 完成的。在 SC12T、TG8T 和 ITG6T 以及 LVT 和 HVT FinFET/CMOS 的所有三个提议的 Ex-OR 设计中，只有 ITG6T 是设计人员的选择，因为它提供了最低功耗和高能量，与其他两种风格的设计相比，改进了选择，而且当考虑到稳健性和可靠性时，SC12T 和 TG8T 设计不能提供完整的输出。ITG6T 设计的微小毛刺是可靠性较低的特性，为此，最好的替代品是 TFET TG8T，它提供抑制过冲和增强的转换速度。从在不同的临界条件和 100 [公式：见文本]mV 的电源电压下执行的多重仿真中，证明了节能电路选项是 SC12T 和 ITG6T Ex-OR 设计，它们已通过陡坡特性进行验证的 TFET 以及这两种设计都提供了可靠性优势。