Approximate arithmetic circuits have been considered as an innovative circuit paradigm with improved performance for error-resilient applications which could tolerant certain loss of accuracy. In this paper, a novel approximate multiplier with a different scheme of partial product reduction is proposed. An analysis of accuracy (measured by error distance, pass rate and accuracy of amplitude) as well as circuit-based design metrics (power, delay and area, etc.) is utilized to assess the performance of the proposed approximate multiplier. Extensive simulation results show that the proposed design achieves a higher accuracy than the other approximate multipliers from the previous works. Moreover, the proposed design has a better performance under comprehensive comparisons taking both accuracy and circuit-related metrics into considerations. In addition, an error detection and correction (EDC) circuit is used to correct the approximate results to accurate results. Compared with the exact Wallace tree multiplier, the proposed approximate multiplier design with the error detection and correction circuit still has up to 15% and 10% saving for power and delay, respectively.

中文翻译：

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具有纠错功能的高能效和高精度近似乘法器

近似算术电路被认为是一种创新的电路范例，具有改进的性能，适用于容错的应用，可以容忍一定的精度损失。在本文中，提出了一种新的近似乘法器，它具有不同的部分乘积减少方案。精度分析（通过误差距离、通过率和幅度精度测量）以及基于电路的设计指标（功率、延迟和面积等）用于评估所提出的近似乘法器的性能。广泛的仿真结果表明，所提出的设计比以前工作中的其他近似乘法器具有更高的精度。此外，在考虑精度和电路相关指标的综合比较下，所提出的设计具有更好的性能。此外，错误检测和校正 (EDC) 电路用于将近似结果校正为准确结果。与精确的华莱士树乘法器相比，所提出的带有错误检测和校正电路的近似乘法器设计仍然分别节省了高达 15% 和 10% 的功耗和延迟。