A cap-less voltage spike detection and correction circuit for flipped voltage follower (FVF)-based low dropout regulator (LDO) is proposed in this paper. The transients in the output voltage are controlled by the pull-up currents [Formula: see text] and [Formula: see text] and pull-down currents [Formula: see text] and [Formula: see text]. These currents are dynamic current sources which are activated only during transient period and noise contributed by these current sources at steady state is zero. These currents increase/decrease based on the intermediate FVF node voltage [Formula: see text]. The proposed circuit detects the output voltage via [Formula: see text] and controls the power MOSFET gate and output capacitances by changing the pull-up and pull-down currents whenever the load changes. The proposed circuit consumes small additional bias current in the steady state and achieves less settling time and output spike voltage. This LDO is simulated using 180[Formula: see text]nm technology and the simulation result shows that the LDO has good load transient response with 190[Formula: see text]ns settling time and 170[Formula: see text]mV voltage spike over 1[Formula: see text]mA to 100[Formula: see text]mA load current range.

中文翻译：

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一种用于低压差稳压器的无电容电压尖峰检测与校正电路

本文提出了一种基于翻转电压跟随器（FVF）的低压差稳压器（LDO）的无电容电压尖峰检测与校正电路。输出电压的瞬态由上拉电流[公式：见正文]和[公式：见正文]和下拉电流[公式：见正文]和[公式：见正文]控制。这些电流是动态电流源，仅在瞬态期间被激活，并且这些电流源在稳态时贡献的噪声为零。这些电流根据中间 FVF 节点电压增加/减少 [公式：见正文]。所提出的电路通过 [公式：见文本] 检测输出电压，并通过在负载变化时改变上拉和下拉电流来控制功率 MOSFET 栅极和输出电容。所提出的电路在稳定状态下消耗很小的额外偏置电流，并实现了更少的建立时间和输出尖峰电压。该 LDO 使用 180[公式：见正文]nm 技术进行仿真，仿真结果表明，LDO 具有良好的负载瞬态响应，建立时间为 190[公式：见正文]ns，电压尖峰超过 170[公式：见正文]mV 1[公式：见正文]mA至100[公式：见正文]mA负载电流范围。