In this article, the fan-out chip-last panel-level packaging for heterogeneous integration is investigated. Emphasis is placed on the design, materials, process, fabrication, and simulation of thermomechanical reliability of a heterogeneous integration of one large chip (10 mm $\times 10$ mm) and two small chips (7 mm $\times 5$ mm) by a fan-out method with a redistribution-layer (RDL)-first substrate fabricated on a 515 mm $\times510$ mm panel. Reliability assessment by thermomechanical simulation includes thermal cycling of the heterogeneous integration of the three-chip package on a printed circuit board (PCB) assembly that is performed by a nonlinear temperature- and time-dependent finite-element simulation.

中文翻译：

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用于异构集成的面板级扇出RDL-First包装

在本文中，研究了用于异种集成的扇出末尾面板级封装。重点放在一个大芯片（10毫米）的异质集成的设计，材料，工艺，制造和热机械可靠性仿真上 $ \次10 $ 毫米）和两个小碎片（7毫米） $ \次5 $ 扇出法，并在515毫米上制造出第一层再分布层（RDL） $ \ times510 $ 毫米面板。通过热机械仿真进行的可靠性评估包括三芯片封装在印刷电路板（PCB）组件上的异质集成的热循环，该循环通过非线性的温度和时间相关的有限元仿真来执行。