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Memory-Logic Hybrid Gate With 3-D Stackable Complementary Latches
IEEE Transactions on Electron Devices ( IF 3.1 ) Pub Date : 2020-08-01 , DOI: 10.1109/ted.2020.3000737
Chieh Lee , Yue-Der Chih , Jonathan Chang , Chrong Jung Lin , Ya-Chin King

In this article, a single-layer complementary latch (CL) and one multilayer CL which are fully compatible with standard FinFET CMOS processes are characterized and their applications are extensively discussed. Through the complementary pair with the 3-D stackable twin-bit resistive random-access memory (RRAM) which consists of a TaON-based resistive film, the CLs feature great area efficiency and stable output responses. By measurement, the characteristics of the 3-D stackable twin-bit RRAM are discussed. Besides, the power, output voltage distribution, and data restoration time of the CLs are analyzed and compared.

中文翻译:

具有 3D 可堆叠互补锁存器的存储器逻辑混合门

在本文中,对与标准 FinFET CMOS 工艺完全兼容的单层互补锁存器 (CL) 和多层 CL 进行了表征,并广泛讨论了它们的应用。通过与由 TaON 基电阻膜组成的 3-D 可堆叠双位电阻随机存取存储器 (RRAM) 的互补对,CL 具有很高的面积效率和稳定的输出响应。通过测量,讨论了 3-D 可堆叠双位 RRAM 的特性。此外,分析比较了CLs的功率、输出电压分布和数据恢复时间。
更新日期:2020-08-01
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