A resolution-independent successive approximation register (SAR) analog to digital converter (ADC) architecture based on a switched capacitor integrator is presented. Digital to analog converter (DAC) architecture uses charge sharing and integration principle for reference generation, using only six unit capacitors for a fully differential version. A 10-bit, 1.8-V and 0.9-MS/s SAR ADC is designed in 180-nm CMOS process. ADC architecture is area efficient when compared with SAR ADC with a binary weighted capacitor array DAC. The architecture is largely parasitic insensitive, also programmable resolution is possible with no hardware overhead.

提出了一种基于开关电容积分器的与分辨率无关的逐次逼近寄存器（SAR）模数转换器（ADC）体系结构。数模转换器（DAC）架构使用电荷共享和积分原理来生成参考电压，全差分版本仅使用六个单元电容器。采用180nm CMOS工艺设计了一个10位，1.8V和0.9MS / s的SAR ADC。与具有二进制加权电容器阵列DAC的SAR ADC相比，ADC架构具有较高的面积效率。该架构在很大程度上对寄生虫不敏感，也可以在没有硬件开销的情况下实现可编程分辨率。