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New digital background calibration method for pipelined ADCs
COMPEL ( IF 0.7 ) Pub Date : 2020-06-04 , DOI: 10.1108/compel-10-2019-0396
Ehsan Zia , Ebrahim Farshidi , Abdolnabi Kosarian

Purpose

Pipelined analog-to-digital converters (ADCs) are widely used in electronic circuits. The purpose of this paper is to propose a new digital background calibration method to correct the capacitor mismatch, finite direct current (DC) gain and nonlinearity of residue amplifiers in pipelined ADCs.

Design/methodology/approach

The errors are corrected by defining new functions based on generalized Newton–Raphson algorithm. Although the functions have analytical solutions, an iterative procedure is used for calibration. To accelerate the calibration process, proper initialization for the errors is identified by using evaluation estimation block and solving inverse matrix.

Findings

Several behavioral simulations of a 12-bit 100MS/s pipelined ADC in MATLAB indicate that signal-to-(noise + distortion) ratio (SNDR) and spurious free dynamic range (SFDR) are improved from 30dB/33dB to 70dB/79dB after calibration. Calibration is achieved in approximately 2,000 clock cycles.

Practical implications

The digital part of the proposed method is implemented on field-programmable gate array to validate the performance of the pipelined ADC. The experimental result shows that the degradation of SNDR, SFDR, integral nonlinearity, differential nonlinearity and effective number of bits is negligible according to fixed-point operation vs floating-point in simulation results.

Originality/value

The novelty of this study is to use Newton–Raphson algorithm combined with appropriate initialization to reduce the number of divisions as well as calibration time, which is suitable in the recent nano-meter complementary metal oxide semiconductor technologies.



中文翻译:

流水线ADC的新数字背景校准方法

目的

流水线式模数转换器(ADC)广泛用于电子电路。本文的目的是提出一种新的数字背景校准方法,以校正流水线ADC中的电容器失配,有限直流(DC)增益和残留放大器的非线性。

设计/方法/方法

通过基于广义牛顿-拉夫森算法定义新函数来纠正错误。尽管这些功能具有解析解,但使用迭代过程进行校准。为了加快校准过程,可以使用评估估计块并求解逆矩阵来确定错误的正确初始化。

发现

在MATLAB中对12位100MS / s流水线ADC进行的若干行为模拟表明,校准后,信噪比(SNDR)和无杂散动态范围(SFDR)从30dB / 33dB提高到70dB / 79dB 。校准大约需要2,000个时钟周期。

实际影响

该方法的数字部分在现场可编程门阵列上实现,以验证流水线ADC的性能。实验结果表明,在仿真结果中,根据定点运算与浮点运算,SNDR,SFDR,积分非线性,微分非线性和有效位数的降级可以忽略不计。

创意/价值

这项研究的新颖之处在于将Newton-Raphson算法与适当的初始化结合使用,以减少分割数和校准时间,这适用于最近的纳米互补金属氧化物半导体技术。

更新日期:2020-06-04
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