Purpose

The purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology.

Design/methodology/approach

Because of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices.

Findings

This study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology.

Originality/value

All the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

中文翻译：

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纳米级器件的泄漏减少技术

目的

本文的目的是提出一种减少泄漏的技术，该技术将适用于互补金属氧化物半导体（CMOS）和鳍式场效应晶体管（FinFET）。功耗将始终是集成电路（IC）设计人员关注的主要问题之一。当前，泄漏功率占总功耗的主导，这是一个严重的问题。毫无疑问，CMOS的规模革命彻底改变了IC行业。相反，晶体管尺寸的缩小却增加了泄漏功率，这是对集成电路工业的重大威胁之一。器件的缩放导致其他器件参数的缩放，其中也包括阈值电压。阈值电压的缩放导致亚阈值电流呈指数增长。所以，研究人员不时为CMOS提出了许多减少泄漏的技术。甚至还引入了其他纳米级器件，例如FinFET，碳纳米管场效应晶体管和隧穿场效应晶体管，FinFET已经成为替代CMOS技术的最有利候选者。

设计/方法/方法

由于其泄漏最少，并且不受短沟道效应的限制，因此逐渐开始取代CMOS。在本文中，作者提出了一种使用CMOS和FinFET等纳米级器件降低电路泄漏的技术。他们将建议的PMOS脚睡眠与现有的减少泄漏的技术（如LECTOR技术，LECTOR FOOTER SLEEP技术）进行了比较。所提出的技术已使用CMOS和FinFET器件实现。这项研究发现，对于CMOS和FinFET器件，所提出的方法降低了平均功率，并降低了泄漏功率。

发现

这项研究发现，对于CMOS和FinFET器件，所提出的方法降低了平均功率并降低了泄漏功率。已经针对提出的技术和现有技术计算了延迟，这证明了提出的技术适合于高速电路应用。作者已经实现了更高阶的门，以验证所提出电路的性能。该方法适用于深亚微米CMOS技术和FinFET技术。

创意/价值

提出了针对CMOS器件或FinFET器件的所有现有技术，但是作者已经对这两种器件都实现了所有技术，并已针对CMOS和FinFET器件对提出的技术进行了验证。