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Hardware accelerated range Doppler algorithm for SAR data processing using Zynq processor
Circuit World ( IF 0.9 ) Pub Date : 2020-07-15 , DOI: 10.1108/cw-02-2020-0031
Hiren K. Mewada , Jitendra Chaudhari , Amit V. Patel , Keyur Mahant , Alpesh Vala

Purpose

Synthetic aperture radar (SAR) imaging is the most computational intensive algorithm and this makes its implementation challenging for real-time application. This paper aims to present the chirp-scaling algorithm (CSA) for real-time SAR applications, using advanced field programmable gate array (FPGA) processor.

Design/methodology/approach

A chirp signal is generated and compressed using range Doppler algorithm in MATAB for validation. Fast Fourier transform (FFT) and multiplication operations with complex data types are the major units requiring heavy computation. Therefore, hardware acceleration is proposed and implemented on NEON-FPGA processor using NE10 and CEPHES library.

Findings

The heuristic analysis of the algorithm using timing analysis and resource usage is presented. It has been observed that FFT execution time is reduced by 61% by boosting the performance of the algorithm and speed of multiplication operation has been doubled because of the optimization.

Originality/value

Very few literatures have presented the FPGA-based SAR imaging implementation, where analysis of windowing technique was a major interest. This is a unique approach to implement the SAR CSA using a hybrid approach of hardware–software integration on Zynq FPGA. The timing analysis propagates that it is suitable to use this model for real-time SAR applications.



中文翻译:

使用 Zynq 处理器进行 SAR 数据处理的硬件加速距离多普勒算法

目的

合成孔径雷达 (SAR) 成像是计算量最大的算法,这使得其实现对于实时应用具有挑战性。本文旨在使用先进的现场可编程门阵列 (FPGA) 处理器,介绍用于实时 SAR 应用的 chirp 缩放算法 (CSA)。

设计/方法/方法

使用 MATAB 中的距离多普勒算法生成和压缩啁啾信号以进行验证。具有复杂数据类型的快速傅立叶变换 (FFT) 和乘法运算是需要大量计算的主要单元。因此,提出并使用NE10和CEPHES库在NEON-FPGA处理器上实现硬件加速。

发现

介绍了使用时序分析和资源使用的算法的启发式分析。据观察,通过提高算法的性能,FFT 执行时间减少了 61%,乘法运算的速度因优化而增加了一倍。

原创性/价值

很少有文献介绍基于 FPGA 的 SAR 成像实现,其中对窗口技术的分析是主要兴趣。这是在 Zynq FPGA 上使用硬件-软件集成的混合方法来实现 SAR CSA 的独特方法。时序分析表明该模型适用于实时 SAR 应用。

更新日期:2020-07-15
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