Purpose

The growing trends in the usage of hand held devices necessitate the need to design them with low power consumption and less area design. Besides, information security is gaining enormous importance in information transmission and data storage technology. In addition, today’s technology world is connected, communicated and controlled via the Internet of Things (IoT). In many applications, the most standard and widely used cryptography algorithm for providing security is Advanced Encryption Standard (AES). This paper aims to design an efficient model of AES cryptography for low power and less area.

Design/methodology/approach

First, the main issues related to less area and low power consumption in the AES encryption core are addressed. To implement optimized AES core, the authors proposed optimized multiplicative inverse, affine transforms and Xtime multipliers functions, which are the core function of AES’s core. In addition, to achieve the high throughput, it uses the multistage pipeline and resource reuse architectures for SBox and Mixcolumn of AES.

Findings

The results of optimized AES architecture have revealed that the multistage pipe line and resource sharing are optimal design model in Field Programmable Gate Array (FPGA) implementation. It could provide high security with low power and area for IoT and wireless sensors networks.

Originality/value

This proposed optimized modified architecture has been implemented in FPGA to calculate the power, area and delay parameters. This multistage pipeline and resource sharing have promised to minimize the area and power.

中文翻译：

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用于物联网应用的 FPGA 上功率和面积优化的 AES 架构的设计和实现

目的

手持设备使用的不断增长的趋势要求设计它们具有低功耗和更小的面积设计。此外，信息安全在信息传输和数据存储技术中变得越来越重要。此外，当今的技术世界通过物联网 (IoT) 进行连接、通信和控制。在许多应用中，用于提供安全性的最标准和最广泛使用的加密算法是高级加密标准 (AES)。本文旨在设计一种低功耗、小面积的 AES 密码学高效模型。

设计/方法/方法

首先，解决了AES加密核心面积小、功耗低的主要问题。为了实现优化的AES核心，作者提出了优化的乘法逆、仿射变换和Xtime乘法器函数，这是AES核心的核心功能。此外，为了实现高吞吐量，它使用了 AES 的 SBox 和 Mixcolumn 的多级管道和资源重用架构。

发现

优化AES架构的结果表明，多级流水线和资源共享是现场可编程门阵列（FPGA）实现中的最佳设计模型。它可以为物联网和无线传感器网络提供低功率和低面积的高安全性。

原创性/价值

这种建议的优化修改架构已在 FPGA 中实现，以计算功率、面积和延迟参数。这种多级管道和资源共​​享已承诺最大限度地减少面积和功率。