Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC.,A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration.,The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms.,The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

中文翻译：

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基于CMOS技术的SAR ADC双比较器/放大器的超低功耗省时电路

逐次逼近寄存器 (SAR) 模数转换器 (ADC) 在低功耗操作方面是众所周知的。为了使其节能省时，科学家们在过去的二十年里一直在努力，它仍然需要研究人员的关注。在实际工作中,SAR ADC中没有同时产生两个比较器输出的机制和电路。,提出了一种小型、低功耗、高能效的双比较器和放大器电路。 SAR ADC 的重要组成部分。主要思想是设计一个多维电路，可以提供两个快速并行比较。通过引入较少数量的 MOSFET 和小尺寸电容器，这三个器件的电路被组合和小型化，无需任何匹配和校准。建议比较器的电源电压为 0.7 V，总功耗为 0.257mW。输入和时钟频率分别为 5 和 50 MHz。由于蜘蛛锁存电路的共享和集中，不需要任何偏移校准和不匹配问题。总失调电压为 0.13 0.31 mV，0.3VDD 至 VDD。所有的元件都是小尺寸和小型化的，使电路具有成本效益和能源效率。比较器的上升和响应时间约为 100 ns。SNDR 从 56 dB 提高到 65 dB，其中放大器的输入参考噪声为 98mVrms。与传统比较器相比，所提出的设计在两种模式（工作和待机）下都没有线性复杂度；它最终旨在和设计用于 11 位 SAR ADC。