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Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit
Journal of Electronic Testing ( IF 0.9 ) Pub Date : 2020-07-19 , DOI: 10.1007/s10836-020-05892-3
Mamoru Ishizaka , Michihiro Shintani , Michiko Inoue

Resistive random-access memory (ReRAM) has several attractive features such as high storage density and high switching frequency with low power consumption. It is hence regarded as the most promising nonvolatile memory material. However, a memristor, which is a primitive component of the ReRAM-based memory, has much lower write endurance. Hence, an error-correcting code (ECC) circuit is indispensable for realizing reliable ReRAM storage. Accordingly, we propose a hybrid CMOS/memristor-based ECC circuit. In the proposed circuit, the blocks with high-frequency write operations are implemented using the conventional CMOS technology and the other blocks are implemented using the memristors to maintain a balance between the area overhead and reliability. Through numerical experiments, we demonstrate that the proposed ECC circuit achieves smaller area and higher reliability than the full memristor-based ECC circuits and achieves much smaller area while preserving the reliability compared with the full CMOS-based ECC circuits.

中文翻译:

基于混合CMOS /忆阻器电路的高效,可靠的纠错码电路

电阻式随机存取存储器(ReRAM)具有一些吸引人的功能,例如高存储密度和高开关频率以及低功耗。因此,它被认为是最有前途的非易失性存储材料。但是,忆阻器是基于ReRAM的内存的原始组件,其写入耐久性要低得多。因此,纠错码(ECC)电路对于实现可靠的ReRAM存储是必不可少的。因此,我们提出了一种基于混合CMOS /忆阻器的ECC电路。在所提出的电路中,具有高频写操作的块是使用常规CMOS技术实现的,而其他块是使用忆阻器实现的,以在面积开销和可靠性之间保持平衡。通过数值实验
更新日期:2020-07-19
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