Abstract As the chip power densities increase radically with scaling, thermal gradients are predicted to become a major reliability concern in interconnects compatible with the 3 nm technology node and beyond. In this study, the impact of temperature gradients on the reliability of Cu nano-interconnects with highly scaled linewidth of 10 nm is simulated using a Korhonen-type modelling framework previously calibrated for electromigration predictions. ∆T dictates the stress distribution at steady state while dT/dx along the interconnect governs the stress evolution rate. It is shown that a linear temperature profile with a ∆T of >25 °C can generate voiding by thermomigration alone in these narrow lines. The adverse impact of thermal gradients by thermomigration and also by thermally induced flux divergence points are explored, showing a 20% drop of jmax in the presence of a ∆T of 10 °C and secondary nucleation sites along the line depending on temperature distribution. Immortality of Cu nano-interconnects to electromigration in the presence of thermal gradients was assessed whereby a thermally adjusted jLc is found relevant depending on the direction of electron flow with respect to temperature gradient.

中文翻译：

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在热梯度下模拟高级铜纳米互连中的应力演化和空洞

摘要 随着芯片功率密度随着缩放而急剧增加，预计热梯度将成为与 3 nm 技术节点及更高技术节点兼容的互连的主要可靠性问题。在这项研究中，温度梯度对具有 10 nm 高度缩放线宽的 Cu 纳米互连的可靠性的影响使用先前为电迁移预测校准的 Korhonen 型建模框架进行了模拟。∆T 决定了稳定状态下的应力分布，而沿互连的 dT/dx 决定了应力演化速率。结果表明，ΔT > 25 °C 的线性温度曲线可以在这些窄线中单独通过热迁移产生空洞。探讨了热迁移和热诱导通量发散点对热梯度的不利影响，显示在存在 10 °C 的 ∆T 和沿线的二次成核位点的情况下，jmax 下降 20%，具体取决于温度分布。评估了在存在热梯度的情况下，Cu 纳米互连对电迁移的不朽性，由此发现热调节的 jLc 与电子流相对于温度梯度的方向相关。