In this paper we identify the dominant contribution to the OFF-state distortion of an MOS transistor coming from the overlap regions applying of device-level harmonic balance simulations in a calibrated TCAD setup. Both overlap ($C_{\mathit{gs}},C_{\mathit{gd}}$) and direct capacitance ($C_{\mathit{ds}}$) are described with novel physics-based models that are, in conjunction with an analytical Volterra series analysis, capable of describing the harmonics. This includes the dependency on process and device design parameters such as gate oxide thickness, DC gate bias and doping profile properties in the gate overlap region. The new model is compared to the overlap models of BSIM and EKV showing superior accuracy in modeling the harmonics qualitatively and quantitatively (within $<3$ dBm for the second and $<5$ dBm for the third harmonic, respectively).

在本文中，我们确定了在校准的TCAD设置中应用设备级谐波平衡仿真产生的，来自重叠区域的MOS晶体管对OFF态畸变的主要贡献。两者重叠（$C_{\mathit{s}}，C_{\mathit{d}}$）和直接电容（$C_{\mathit{ds}}$用新颖的基于物理学的模型进行了描述，该模型结合了Volterra级数分析法，能够描述谐波。这包括对工艺和器件设计参数的依赖性，例如栅极氧化层厚度，直流栅极偏置和栅极重叠区域中的掺杂分布特性。将新模型与BSIM和EKV的重叠模型进行比较，显示出在定性和定量建模谐波（在$<3$ dBm为第二和 $<5$ 三次谐波分别为dBm）。