The growing sophistication of cyber attacks, vulnerabilities in high computing systems and increasing dependency on cryptography to protect our digital data make it more important to keep secret keys safe and secure. Few major issues on secret keys like incorrect use of keys, inappropriate storage of keys, inadequate protection of keys, insecure movement of keys, lack of audit logging, insider threats and non-destruction of keys can compromise the whole security system dangerously. In this article, we have proposed and implemented an isolated secret key memory which can log life cycle of secret keys cryptographically using blockchain (BC) technology. We have also implemented a special custom bus interconnect which receives custom crypto instruction from Processing Element (PE). During the execution of crypto instructions, the architecture assures that secret key will never come in the processor area and the movement of secret keys to various crypto core is recorded cryptographically after the proper authentication process controlled by proposed hardware based BC. To the best of our knowledge, this is the first work which uses blockchain based solution to address the issues of the life cycle of the secret keys in hardware platform. The additional cost of resource usage and timing complexity we spent to implement the proposed idea is very nominal. We have used Xilinx Vivado EDA tool and Artix 7 FPGA board.

中文翻译：

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基于区块链的可重构平台密钥生命周期审计器

网络攻击的日益复杂、高计算系统中的漏洞以及对加密技术的日益依赖以保护我们的数字数据，使得保护密钥安全变得更加重要。密钥的不正确使用、密钥存储不当、密钥保护不足、密钥移动不安全、缺乏审计日志、内部威胁和密钥未破坏等密钥方面的重大问题很少会危及整个安全系统。在本文中，我们提出并实现了一种隔离的密钥存储器，它可以使用区块链 (BC) 技术以加密方式记录密钥的生命周期。我们还实现了一个特殊的自定义总线互连，它接收来自处理元件 (PE) 的自定义加密指令。在执行加密指令期间，该架构确保秘密密钥永远不会进入处理器区域，并且在由提议的基于硬件的 BC 控制的正确身份验证过程之后，以密码方式记录秘密密钥到各种加密核心的移动。据我们所知，这是第一个使用基于区块链的解决方案来解决硬件平台中密钥生命周期问题的工作。我们为实现所提议的想法而花费的资源使用和时间复杂度的额外成本非常小。我们使用了 Xilinx Vivado EDA 工具和 Artix 7 FPGA 板。这是第一个使用基于区块链的解决方案来解决硬件平台中密钥生命周期问题的工作。我们为实现所提议的想法而花费的资源使用和时间复杂度的额外成本非常小。我们使用了 Xilinx Vivado EDA 工具和 Artix 7 FPGA 板。这是第一个使用基于区块链的解决方案来解决硬件平台中密钥生命周期问题的工作。我们为实现所提议的想法而花费的资源使用和时间复杂度的额外成本非常小。我们使用了 Xilinx Vivado EDA 工具和 Artix 7 FPGA 板。