In this work, with the help of extensive technology computer-aided design simulations, we report a comprehensive study of MOSFET based circuit design using ultra-thin body III-V on-insulator (OI) CMOS transistors. We demonstrate the circuit performance of III-V CMOS by combining InAs-OI n-channel and GaAs-OI junction-less p-channel transistors. The performance metrics of different circuits designed using III-V transistors are also compared with III-V/Germanium and Silicon-on-insulator (SOI) based CMOS logic. CMOS inverter circuit designed using III-V/Ge (InAs-OI/GeOI) CMOS shows 51% and 17% reduction in rise and fall time compared to SOI CMOS. The oscillation frequency of the ring oscillator designed using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) CMOS logic is approximately three times and two times higher than SOI based design. The unity-gain bandwidth of the inverting amplifier using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) architecture is 22 times and 9.5 times higher compared to SOI CMOS based circuit. Static noise margin (SNM) of conventional six-transistor (6-T) SRAM cell is also analyzed during hold operation. Due to the poor electrostatic integrity of III-V transistors, degradation in SNM is observed compared to its SOI counterparts. The cascode low noise amplifier (LNA) circuit designed using InAs-OI transistor shows the higher gain and low noise figure at the same operating frequency compared to the SOI transistor-based LNA.

在这项工作中，借助广泛的技术计算机辅助设计仿真，我们报告了使用超薄体III-V绝缘体（OI）CMOS晶体管的基于MOSFET电路设计的全面研究。我们通过结合InAs-OI n沟道和GaAs-OI无结p沟道晶体管来展示III-V CMOS的电路性能。还将使用III-V晶体管设计的不同电路的性能指标与基于III-V /锗和绝缘体上硅（SOI）的CMOS逻辑进行了比较。使用III-V / Ge（InAs-OI / GeOI）CMOS设计的CMOS反相器电路显示51 ％和17 ％与SOI CMOS相比，减少了上升和下降时间。使用III-V / Ge（InAs-OI / GeOI）和III-V（InAs-OI / GaAs-OI）CMOS逻辑设计的环形振荡器的振荡频率大约是基于SOI的设计的三倍和两倍。与基于SOI CMOS的电路相比，使用III-V / Ge（InAs-OI / GeOI）和III-V（InAs-OI / GaAs-OI）架构的反相放大器的单位增益带宽分别高22倍和9.5倍。在保持操作期间，还分析了常规六晶体管（6-T）SRAM单元的静态噪声容限（SNM）。由于III-V晶体管的不良静电完整性，与SOI同类晶体管相比，SNM出现了退化。