Abstract Spin-transfer torque (STT)-magnetic random access memory (MRAM) requires yield-aware design for hybrid magnetic-CMOS integration. In this paper, a novel cycle-sensing margin enhancement (CSME) scheme with pMOS assisted voltage-type sense amplifier (p-VSA) is proposed to alleviate imperfect process induced performance fluctuations. With iterated charging-discharging through non-volatile data path and reference path, read margin can be significantly improved thanks to the enlarged sensing window. Simulation is performed using MTJ compact model and an industrial 28-nm CMOS process. Results show that with 0.6 V supply voltage ~14.1% read yield improvement can be realized at 50% tunnel magnetoresistance (TMR) ratio comparing to conventional VSA.

中文翻译：

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CSME：一种用于高良率 STT-MRAM 的新型周期感应裕度增强方案

摘要 自旋转移矩 (STT)-磁性随机存取存储器 (MRAM) 需要对混合磁性-CMOS 集成进行良率感知设计。在本文中，提出了一种具有 pMOS 辅助电压型感测放大器 (p-VSA) 的新型周期感测裕度增强 (CSME) 方案，以减轻不完美的工艺引起的性能波动。通过非易失性数据路径和参考路径的反复充放电，由于扩大了感应窗口，可以显着提高读取裕度。使用 MTJ 紧凑模型和工业 28-nm CMOS 工艺执行仿真。结果表明，与传统 VSA 相比，0.6 V 电源电压可在 50% 隧道磁阻 (TMR) 比率下实现 ~14.1% 的读取良率提高。