This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Accelerated operation of neuromorphic circuits and highly-parallel digital data buses between the full-custom neuromorphic part and the PPU require custom methodologies to close the digital signal timing at the interfaces. Novel extensions to the standard digital physical implementation design flow are highlighted. We present early results from the first full-size BrainScaleS-2 ASIC containing 512 neurons and 130 K synapses, demonstrating the successful application of these methods. An application example illustrates the full functionality of the BrainScaleS-2 hybrid plasticity architecture.

本文介绍了为BrainScaleS-2 65 nm ASIC设计而开发的验证和实现方法。第二代BrainScaleS芯片是混合信号设备，在完全定制的模拟神经形态电路与两个具有SIMD扩展功能的通用微处理器（PPU）之间紧密耦合，可实现片上学习和可塑性。提出了用于高度可参数化的模拟神经元和突触电路的自动化分析和预胶带校准以及数字逻辑和软件堆栈的硬件-软件共同开发的仿真方法。完全定制的神经形态部分与PPU之间的神经形态电路和高度并行的数字数据总线的加速操作需要定制方法来关闭接口处的数字信号时序。突出了对标准数字物理实施设计流程的新颖扩展。我们从包含512个神经元和130 K突触的第一个全尺寸BrainScaleS-2 ASIC提出了早期结果，证明了这些方法的成功应用。一个应用示例说明了BrainScaleS-2混合可塑性体系结构的全部功能。