We present a machine learning (ML) framework to improve the use of computing resources in the FPGA compilation step of a commercial FPGA-based logic emulation flow. Our ML models enable highly accurate predictability of the final place and route design qualities, runtime, and optimal mapping parameters. We identify key compilation features that may require aggressive compilation efforts using our ML models. Experiments based on our large-scale database from an industry’s emulation system show that our ML models help reduce the total number of jobs required for a given netlist by 33%. Moreover, our job scheduling algorithm based on our ML model reduces the overall time to completion of concurrent compilation runs by 24%. In addition, we propose a new method to compute “recommendations” from our ML model to perform re-partitioning of difficult partitions. Tested on a large-scale industry system on chip design, our recommendation flow provides additional 15% compile time savings for the entire system on chip. To exploit our ML model inside the time-critical multi-FPGA partitioning step, we implement it in an optimized multi-threaded representation.

中文翻译：

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通过机器学习改进基于 FPGA 的逻辑仿真系统

我们提出了一个机器学习 (ML) 框架，以改进基于商业 FPGA 的逻辑仿真流程的 FPGA 编译步骤中计算资源的使用。我们的 ML 模型能够高度准确地预测最终布局和布线设计质量、运行时间和最佳映射参数。我们确定了可能需要使用我们的 ML 模型进行积极编译工作的关键编译功能。基于我们来自行业仿真系统的大型数据库的实验表明，我们的 ML 模型有助于将给定网表所需的作业总数减少 33%。此外，我们基于 ML 模型的作业调度算法将完成并发编译运行的总时间减少了 24%。此外，我们提出了一种新方法来从我们的 ML 模型中计算“推荐”，以执行困难分区的重新分区。在大规模行业片上系统设计上进行了测试，我们的推荐流程为整个片上系统额外节省了 15% 的编译时间。为了在时间关键的多 FPGA 分区步骤中利用我们的 ML 模型，我们以优化的多线程表示来实现它。