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A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture
Circuits, Systems, and Signal Processing ( IF 2.3 ) Pub Date : 2020-02-18 , DOI: 10.1007/s00034-020-01371-4
Gopal Raut , Ambika Prasad Shah , Vishal Sharma , Gunjan Rajput , Santosh Kumar Vishvakarma

Reconfigurability is an important capability that provides flexibility in computing architecture and low-power technique. It is challenging in digital-in-concept for designing smart analog circuits operated on low power. This work presents a low-power, low-noise, and high-speed multistage feed-forward reconfigurable comparator for medium-to-high-speed analog-to-digital converter. A power-efficient reconfigurable comparator design at 180 nm is presented with a new power reduction and offset compensation technique. The proposed dynamic latch-based 2-stage comparator gives an 83.2% power saving compared with a 3-stage comparator. The reduced number of active stages in comparator lowers the load capacitance to the post-amplifier and the power consumption. The 2-stage comparator gives a high slew rate, low power consumption, and better result at a Nyquist rate of 2.4 GS/s as compared with the previous state of the art. We have also proposed the reconfigurable multistage comparator, which gives the features of both 2-/3-stage comparators. We have performed the post-layout simulation to validate the design for process variation and mismatch with proposed circuit and compared with state of the art. Further, the voltage gain is 100 dB with power supply 1.8 V while consuming 523.4 $$\upmu $$ μ W and 86.15 $$\upmu $$ μ W for 3-stage and 2-stage comparator, respectively.

中文翻译:

适用于 ADC 架构的 2.4-GS/s 高能效、高分辨率可重构动态比较器

可重构性是在计算架构和低功耗技术中提供灵活性的重要能力。设计低功耗智能模拟电路的数字概念具有挑战性。这项工作提出了一种用于中高速模数转换器的低功耗、低噪声和高速多级前馈可重构比较器。一种 180 nm 的高能效可重配置比较器设计采用了新的功率降低和偏移补偿技术。与 3 级比较器相比,建议的基于动态锁存器的 2 级比较器可节省 83.2% 的功率。比较器中活动级数量的减少降低了后置放大器的负载电容和功耗。2 级比较器提供高转换率、低功耗、与之前的技术水平相比,在 2.4 GS/s 的奈奎斯特速率下获得更好的结果。我们还提出了可重构多级比较器,它提供了 2-/3 级比较器的特性。我们已经执行了布局后模拟,以验证设计的工艺变化和与建议电路的不匹配,并与最先进的技术进行比较。此外,对于 3 级和 2 级比较器,电压增益为 100 dB,电源为 1.8 V,同时分别消耗 523.4 $\upmu $$ μ W 和 86.15 $$\upmu $$ μ W。我们已经执行了布局后模拟,以验证设计的工艺变化和与建议电路的不匹配,并与最先进的技术进行比较。此外,对于 3 级和 2 级比较器,电压增益为 100 dB,电源为 1.8 V,同时分别消耗 523.4 $\upmu $$ μ W 和 86.15 $$\upmu $$ μ W。我们已经执行了布局后模拟,以验证设计的工艺变化和与建议电路的不匹配,并与最先进的技术进行比较。此外,对于 3 级和 2 级比较器,电压增益为 100 dB,电源为 1.8 V,同时分别消耗 523.4 $\upmu $$ μ W 和 86.15 $$\upmu $$ μ W。
更新日期:2020-02-18
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