Energy efficiency is a critical design objective in deep learning hardware, particularly for real-time machine learning applications where the processing takes place on resource-constrained platforms. The inherent resilience of these applications to error makes voltage scaling an attractive method to enhance efficiency. Timing error probability models are proposed in this article to better understand the effects of voltage scaling on error rates and power consumption of multiply-accumulate units. The accuracy of the proposed models is demonstrated via Monte Carlo simulations. These models are then used to quantify the related tradeoffs without relying on time-consuming hardware-level simulations. Both modern FinFET and emerging tunneling field-effect transistor (TFET) technologies are considered to explore the dependence of the effects of voltage scaling on these two technologies.

中文翻译：

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电压缩放乘法累加单元的误差概率模型

能源效率是深度学习硬件的关键设计目标，特别是对于在资源受限平台上进行处理的实时机器学习应用程序。这些应用对错误的固有弹性使电压缩放成为提高效率的一种有吸引力的方法。本文提出了时序错误概率模型，以更好地理解电压缩放对乘法累加单元的错误率和功耗的影响。通过蒙特卡罗模拟证明了所提出模型的准确性。然后使用这些模型来量化相关的权衡，而无需依赖耗时的硬件级模拟。